Regarding the tutorial for Writing Code in Edk

Dear Sir,
I am quite new to EDK. I am learning to write code in EDK. Can anybody Please let me know the tutorials for writing code in edk(Learning syntax for it) ?

I am using EDK 10.1

hi check xilinx software folder
Xilinx\12.4\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers
check the core examples given...
for other examples go to this link
Cosmiac - Configurable Space Microsystems Innovations & Applications Center
FPGA Developer: Timer with Interrupts in EDK10-1

Please clarify. SW code or HW code
EDK is used to make embedded system using Xilinx FPGA. It has facilities to make HW & SW. to build a HW; you don’t need to write code except UCF file or some setting files. Most HW design is done by GUI in the EDK.
If you want to write IP core, it is recommended to use ISE.
To write SW you need to write C code.

HI,

My application is to receive 10 data from the RS-232 in Microblaze and to process the received data. tats it. for doing this, i have to learn basic code for doing this. which is preferable to me?

make a project in the EDK. you need the following IP cores as minimum system
1- Microblaze
2- LMB
3- UART Lite
4- BRAM
it is suggested to use BSB to make them

in the application section, you can add ro edit existing .c file to do your application.
you can use inbyte() function to read data form UART Lite or using the following macros:
/* UART Lite register offsets */

#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */

/* control register bit positions */

#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */

/* status register bit positions */

#define XUL_SR_PARITY_ERROR 0x80
#define XUL_SR_FRAMING_ERROR 0x40
#define XUL_SR_OVERRUN_ERROR 0x20
#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */

/* the following constant specifies the size of the FIFOs, the size of the
* FIFOs includes the transmitter and receiver such that it is the total number
* of bytes that the UART can buffer
*/
#define XUL_FIFO_SIZE 16

/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
* per instance basis
*/
#define XUL_STOP_BITS 1

/* Parity definitions
*/
#define XUL_PARITY_NONE 0
#define XUL_PARITY_ODD 1
#define XUL_PARITY_EVEN 2


/****************************************************************************/
/**
*
* Set the contents of the control register. Use the XUL_CR_* constants defined
* above to create the bit-mask to be written to the register.
*
* @param BaseAddress is the base address of the device
* @param Mask is the 32-bit value to write to the control register
*
* @return None.
*
* @note C-style Signature:
* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask);
*
*****************************************************************************/
#define XUartLite_mSetControlReg(BaseAddress, Mask) \
XIut32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask))


/****************************************************************************/
/**
*
* Get the contents of the status register. Use the XUL_SR_* constants defined
* above to interpret the bit-mask returned.
*
* @param BaseAddress is the base address of the device
*
* @return A 32-bit value representing the contents of the status register.
*
* @note C-style Signature:
* u32 XUartLite_mGetStatusReg(u32 BaseAddress);
*
*****************************************************************************/
#define XUartLite_mGetStatusReg(BaseAddress) \
XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)

/****************************************************************************/
/**
*
* Check to see if the receiver has data.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the receiver is empty, FALSE if there is data present.
*
* @note C-style Signature:
* int XUartLite_mIsReceiveEmpty(u32 BaseAddress);
*
*****************************************************************************/
#define XUartLite_mIsReceiveEmpty(BaseAddress) \
((XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
XUL_SR_RX_FIFO_VALID_DATA)

/****************************************************************************/
/**
*
* Check to see if the transmitter is full.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the transmitter is full, FALSE otherwise.
*
* @note C-style Signature:
* int XUartLite_mIsTransmitFull(u32 BaseAddress);
*
*****************************************************************************/
#define XUartLite_mIsTransmitFull(BaseAddress) \
((XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
XUL_SR_TX_FIFO_FULL)

/****************************************************************************/
/**
*
* Check to see if the interrupt is enabled.
*
* @param BaseAddress is the base address of the device
*
* @return TRUE if the interrupt is enabled, FALSE otherwise.
*
* @note C-style Signature:
* int XUartLite_mIsIntrEnabled(u32 BaseAddress);
*
*****************************************************************************/
#define XUartLite_mIsIntrEnabled(BaseAddress) \
((XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
XUL_SR_INTR_ENABLED)

/****************************************************************************/
/**
*
* Enable the device interrupt. We cannot read the control register, so we
* just write the enable interrupt bit and clear all others. Since the only
* other ones are the FIFO reset bits, this works without side effects.
*
* @param BaseAddress is the base address of the device
*
* @return None.
*
* @note C-style Signature:
* void XUartLite_mEnableIntr(u32 BaseAddress);
*
*****************************************************************************/
#define XUartLite_mEnableIntr(BaseAddress) \
XUartLite_mSetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)

/****************************************************************************/
/**
*
* Disable the device interrupt. We cannot read the control register, so we
* just clear all bits. Since the only other ones are the FIFO reset bits,
* this works without side effects.
*
* @param BaseAddress is the base address of the device
*
* @return None.
*
* @note C-style Signature:
* void XUartLite_mDisableIntr(u32 BaseAddress);
*
*****************************************************************************/
#define XUartLite_mDisableIntr(BaseAddress) \
XUartLite_mSetControlReg((BaseAddress), 0)