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Test Patterns using path delay models for same circuit in different corners

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dhaval4987

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I have transistor level spice netlist of a circuit and model files for different corners.

I want to generate test patterns for path delay model for the same. I think I need to learn Tetramax. Does anyone have any tutorial/manuals for a beginner?

Also- Does it take transistor level netlists for generating patterns? I am wondering if it is able to read different corner model files and generate different patterns for the same circuit.

Please help.
 

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