rowan.bradley
Junior Member level 1
I have a system using an 80C320 microprocessor running at 12MHz clock. It uses a lot of memory mapped IO (8-bit data, 16-bit address). I want to implement automatic testing for this system, and I'm thinking of adding a second processor (probably an ARM of some sort) which can read and write to the addresses normally used by the IO registers. To do this the RAM needs to be "dual port", i.e. the 80C320 and the new processor both need asynchronously to be able to read and write the memory locations. Normally any particular block of memory will only be written to by the 80C320 and read by the ARM (output registers), or written to by the ARM and read by the 80C320 (input registers).
Since the 80C320 is quite slow, I think it should be possible to use normal single port SRAM and multiplex the reading and writing from the two processors. Also since I'm writing the ARM software from scratch I can have it wait if the SRAM is busy when it wants to read or write. The 80C320 will not wait however - the data must be available within the access time when it asks for it.
Using an FPGA for the multiplexing logic seems a promising idea. However I'm not familiar with modern day FPGAs. Can you recommend which type of FPGA and design software will be best suited to this task, and will allow me to get this done as quickly as possible? It will need to do something like:
Even better, has anyone done anything like this before? Does anyone have a design I could use as a basis for my solution?
Thanks - Rowan
Since the 80C320 is quite slow, I think it should be possible to use normal single port SRAM and multiplex the reading and writing from the two processors. Also since I'm writing the ARM software from scratch I can have it wait if the SRAM is busy when it wants to read or write. The 80C320 will not wait however - the data must be available within the access time when it asks for it.
Using an FPGA for the multiplexing logic seems a promising idea. However I'm not familiar with modern day FPGAs. Can you recommend which type of FPGA and design software will be best suited to this task, and will allow me to get this done as quickly as possible? It will need to do something like:
- generate a clock to time the read/write cycles and the multiplexing
- alternate between the two address/data buses
- latch the address and (for writes) data from either bus when a Read Enable or Write Enable is present
- apply the address and data (for writes) from the latches to the SRAM in the right part of the timing cycle
- apply write enable or read enable to the SRAM at the right time
- for reads, latch the data from the SRAM at the right time
- for reads, apply the data in the latch to the correct data bus while Read Enable is present
Even better, has anyone done anything like this before? Does anyone have a design I could use as a basis for my solution?
Thanks - Rowan