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Problem with difference in driving strenths of NMOS and PMOS transistors

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Ravinder487

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Problem with difference in driving strengths of NMOS and PMOS transistors

Hi all,
I'm designing digital circuit(consisting of MUXes and full Adder) for my ADC. At the output of my digital block I'm getting postive glitches. It seems because of difference in mobiities of NMOS and PMOS transistors. And I've verified by varying W/L of PMOS transistor.
To eliminate this I've two ideas
1) To precisely find Wp/Wn ratio for tphl=tplh for an inverter and size appropriately all the logic gates(NAND NOR etc).
2)or at the end of digital logic place a buffer-with first inverter having strong PMOS and second inverter with strong NMOS.
Which of these two method seems to be logical?
Does the same effect is seen in other logic blocks?, if so then how they will manage ?
 
Last edited:

hi Ravinder

I'm not sure I am getting what you mean by "positive glitches" caused by "difference in mobiities of NMOS and PMOS transistors"; can you elaborate and perhaps post an image of the glitches?
 

Further on,
even though you do design with very accurate ratios and relationships between the P and N-type transistors, the mismatch variations would kill that (1) approach anyway. So, from that perspective number (2) would make more sense - but also for me the concept "positive glitches" is puzzling.
 

It would be much better to capture the waveform containing the glitches in order to illustrate your problem.
 

Re: Problem with difference in driving strengths of NMOS and PMOS transistors

Anther way to think about it:
It might be caused by no dead time for switching.
To solve it, a resistor can be series connected at the front stage inverter. And NMOS/PMOS gate at the following stage are connected to the different ends of the resistor.
It helps to form some dead time.
Ravinder487 said:
Hi all,
I'm designing digital circuit(consisting of MUXes and full Adder) for my ADC. At the output of my digital block I'm getting postive glitches. It seems because of difference in mobiities of NMOS and PMOS transistors. And I've verified by varying W/L of PMOS transistor.
To eliminate this I've two ideas
1) To precisely find Wp/Wn ratio for tphl=tplh for an inverter and size appropriately all the logic gates(NAND NOR etc).
2)or at the end of digital logic place a buffer-with first inverter having strong PMOS and second inverter with strong NMOS.
Which of these two method seems to be logical?
Does the same effect is seen in other logic blocks?, if so then how they will manage ?
Click to expand...
 
Thanks all,
I'm attaching 2 plots from transient analysis
in first plot 'out' is my final ADC output (output of mux,M1 ('/net0136') followed by buffer),2 inputs of mux are '/I21/net042' and '/I21/net037'(output from another Mux,M2) with 'fin' as control signal. '/net0136' is output of mux.


In second plot inputs of Mux2(4:1,with S0,S1,S2,S3 as control signals) with superimposed control signals over corresponding inputs is shown.
 

Your problem it relative timing between your control Sx signals and whatever signal(s) 'launches' the data change in the MUX inputs (perhaps a master clock), your select signal have small overlaps in time with the edges of data changing

Your options are:
- ignore it and sample in the 'middle' (e.g. your MUX inputs change on the rising edge of a master clock, then you sample the MUX outputs on the falling edge)
OR
- non-overlapping select signals (might be a waste of power if you are caring for it)
OR
- use buffers to speed up and slow down paths (not easy in this case and probably not robust)
 
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