HELP me with my data format converder please?

It is receiving data from a gyroscope, the format is a synchronized signal, when the gyro-clock has pulses the data is valid. A whole frame is 32 bits. then the clock goes zero for a little period.
The data is saved to a vector and it's sending the data through RS232 format to a computer.
The question is that it should only send after receiving a 32 bit. I use the state machine. I wanna make it as simple as I can so I only define 2 states: receive and send.
But the simulation seems the state never jumped from the receive state to send state. I am alone on this now and can't find a way to solve it T_T...
I'm a VHDL starter so my coding style might seems ridiculously immature...

here's my code:

entity Main is
port (gyroclk : in std_logic;
gyrodata : in std_logic;
seclk : in std_logic;
serial: out std_logic
);
end Main;

architecture Behavioral of Main is
type iState is (send, receive);
signal Cache: std_logic_vector ( 0 to 54 ):="0100000001100000000011000000000110000000001100000000011";
signal n: integer range 0 to 31:=0;
signal i: integer range 0 to 54:=0;
signal state: iState;
begin

state_controlrocess(seclk, gyroclk, n, i)
begin
if i=0 then
state<=RECEIVE;
end if;
case state is
when RECEIVE =>
if (n=31) then
state<=SEND;
end if;

when SEND =>
if (i=54) then
state<=RECEIVE;
end if;

when others => null;
end case;
end process;

receive_gyrorocess(gyroclk)
begin
if state=RECEIVE then
if gyroclk'event and gyroclk='1' then
if n>=0 and n<7 then
Cache(n+2)<=gyrodata;
elsif n>=7 and n<14 then
Cache(n+6)<=gyrodata;
elsif n>=14 and n<21 then
Cache(n+10)<=gyrodata;
elsif n>=21 and n<28 then
Cache(n+14)<=gyrodata;
elsif n>=28 and n<32 then
Cache(n+18)<=gyrodata;
end if;
if n<31 then
n<=n+1;
elsif n=31 then
n<=0;

end if;
end if;
end if;
end process;

send_RS232rocess(seclk)
begin
if state=SEND then
if seclk'event and seclk='1' then
serial<=Cache(i);
if i <54 then
i<=i+1;
elsif i=54 then
i<=0;
end if;
end if;
elsif state=RECEIVE then
serial<='1';
end if;
end process;

end Behavioral;

fist off, you need to put the state signal in the sensitivity list for the state_control process.

Thanks! It helps, seems now the send process is functional, but in the simulation an error still occured to make it stop.
-------------
Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value in File "F:/Fredrich/Desktop/Final Design/Gyro_RS232/Gyro_RS232/Main.vhd" Line 96. Please correct this code in order to advance past the current simulation time.

the code is
if seclk'event and seclk='1' then
I have already exchanged the position of it with upper level 'if state=SEND then'
but the problem still exist...but it stopped in the simulation when it should be reading, not sending...

I added two pictures, the first is the simulation of the expected input (2nd line) and output(4th line), others are the clock.
and the second is this error waveform.
the expected waveform is my previous try, but that code can only achieve one time of transfer, the second round the output will not response for I didn't use the state machine to jump back to the original receive state. But I use the state machine now, so many problems occured...