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galant said:Use the following tcl commands.
"probe -shm -all"
It can dump the all signals in verilog-xl. You can have a try in Model-sim.
xmizi said:use:
initial
begin
$dumpfile("./***.vcd");
$dumpvars;
end
you can also specify the signals and level of hierarchical in the $dumpvars.
Then use debussy to translate vcd to fsdb or running power analysis or whatever you want with the vcd file
VCD is usually much bigger than fsdb etc.
roger said:What I mean is I wanna to start dumping when some signals
are active. I think you can not use run 20 ??sec, vcd file ...
because we don't know exactly the time when signals are active.
Hopt to share your idea.tks!