AHDL documentation and LCELL info

ahdl lcell

I have been lately working with an @ltera ACEX1K50 based design where the chip should be fast enough, but tooling produces lousy results. I had a related question earlier and received a valuable hint from ngjh (Many Thanks!)

But the next step is that in spite of search at @ltera web site and a question to their support I still find it difficult to find good documentation regarding LCELL and CARRY primitives. I would appreciate documents or links to such regarding those primitives.

I know portability of code is reduced by using such vendor-specific things, but it should be no major issue if I manage to keep those parts isolated in certain components. And I believe the chip will not be changed during lifetime of this particular product anyway.

Additionaly, it seems that by using AHDL instead of VHDL for those speed critical parts, I can get better and more explicit control over the generated logic. Therefore I really wonder if there is a good document or book somewhere covering AHDL, too.

Thanks for any and all help in beforehand,

ted

lcell what is

It's me again,

Check under 'Functional Descriptions' of the 'ACEX 1K Programmable Logic Device Family Data Sheet' at altera's website. There, you can find information regarding the internal construction of the ACEX.

A LCELL is implemented using one logic element (LE). Refer to figure at page 16, I think what happen is the LCELL's input occupies one of the four LUT's inputs and goes through the Register Bypass wire to the output.

Regarding the CARRY and CASCADE primitives, they are a sort of way to
minimise delays. Imagine the scenario where an XOR function required 8 LEs. With CARRY primitives used, all LEs within an LAB can be chained together. Without the primitive, LEs might be scattered around a few LABs, hence, increasing delays. I hope you can understand what i am trying to say :lol: .

You may also looks for more information at Help file provided by Maxplus or Quartus.

I havent used AHDL b4. You may be right. However, you should be able to obtain a similar level of control using VHDL. Just make sure your code is written at low level.

According to Altera, AHDL manual can be purchased from any Altera distributor.

The AHDL is like ABEL language, it can get better and more explicit control over the generated logic, but it is too waste time and the simulating is a problem if your design is not simple