Verilog-A symbol generation

The first time I create a verilog-a file, when I close it, it will remind of creating a symbol. But if I modify the file, it won't remind me any more. Any one know how to modify the symbol after you change the file?

I assume you've created your file under the Cadence environment. Is that correct? In that case, in the library manager you should 2 view in the cell you created. One is the veriloga view, the other the symbol you first created. You can edit directly this symbol view to match your new veriloga.
You might also need to check the CDF database. Sometimes it is not updated correctly meaning you will have trouble at netlisting.
From the icfb "Tools" menu, select the CDF->Edit tag. Check that all the pins are order described for the veriloga row. If you need to change, be sure to set "CDF type" to "base" (the default is "effective").

how do you check the pins in CDF?
I do come into problem when net listing.

---------- Post added at 02:37 ---------- Previous post was at 02:35 ----------

one more problem is that, when I modify the verilog-a file, cadence seems not to check if there is any error.

Form the icfb window, select the Tools->CDF->Edit menu. Set the "CDF type" option to "base".
Fill in your lib name and cell name (or you can use the "Browse" button to open a lib manager adnd select the cell).
After enterring the cell name lots of information should appear.
In the "Simulation Information part" (the second part), you have the different simulators supported by your version of Cadence, with the pin list. For veriloga, the pin list should be at leat in the "spectre" part. If not (happens when copying cells sometimes) you need to add it.

However this data should be automatically generated after editing your verilog. But if the syntax is not checked, it means there is another problem. Try to check the error messages and also see with your site admin (Cadence version and bugs).