zhipeng
Member level 1
I am using Verilog-A to generate a carrier-frequency stimulus to an power amplifier in virtuoso schematics, but saw a mysterious frequency shift in the stimulus when I run spectre simulation. It reduces to a basic test case where,
parameter real omega = 2* `M_PI *20e9;
...
V(pure_sine) <+ sin(omega * $abstime);
V(test) <+ (omega * $abstime);
...
The waveform of V(test) looks as if omega was 2*`M_PI *(20e9 - 5e4) instead of 2*`M_PI *20e9. The generated carrier frequency stimulus is now (20GHz-50kHz) instead of 20GHz. Somehow, the accuracy reduced from 32-bits to roughly 18-bits.
Anyone knows how to force Verilog-A to be 32-bit accurate in generating a sine wave?
parameter real omega = 2* `M_PI *20e9;
...
V(pure_sine) <+ sin(omega * $abstime);
V(test) <+ (omega * $abstime);
...
The waveform of V(test) looks as if omega was 2*`M_PI *(20e9 - 5e4) instead of 2*`M_PI *20e9. The generated carrier frequency stimulus is now (20GHz-50kHz) instead of 20GHz. Somehow, the accuracy reduced from 32-bits to roughly 18-bits.
Anyone knows how to force Verilog-A to be 32-bit accurate in generating a sine wave?