lostinxlation
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Compile directtive and conditional instantiation - Verilog
I have a module that instantiates a cell based on the input value and I so far have no success. I wonder if someone can shed light on it.
let's say the module instanitates a PAD0 if SEL is 0, and PAD1 if SEL is 1.
This module is instantiated on the upper level with either 0 or 1 on SEL.
The issue is the tool doesn't properly pick PAD0 or PAD1 when I run a simulation. I guess passing the information between a compile directive and module ports is the issue, and I don't know if it's even possible, but if anyone knows a good solution for this, appreciate your input.
I have a module that instantiates a cell based on the input value and I so far have no success. I wonder if someone can shed light on it.
let's say the module instanitates a PAD0 if SEL is 0, and PAD1 if SEL is 1.
Code:
module pad_drvr (IN, OUT, SEL);
input IN, SEL;
output OUT;
`define A (SEL==1'b0)
`ifdef A
PAD0 (IN, OUT);
`else
PAD1 (IN, OUT);
`end
endmoduleThis module is instantiated on the upper level with either 0 or 1 on SEL.
Code:
pad_drvr (in0, out0, 1'b0);
pad_drvr (in1, out1, 1'b1);
.....
...The issue is the tool doesn't properly pick PAD0 or PAD1 when I run a simulation. I guess passing the information between a compile directive and module ports is the issue, and I don't know if it's even possible, but if anyone knows a good solution for this, appreciate your input.
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