Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Is $signed() task is synthesizable in verilog 2001?

Status
Not open for further replies.

gsdeshpande

Newbie level 2
Joined
May 19, 2008
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,291
Is $signed() /$unsigned() synthesizable in verilog?
 

Hi, yes and it is even recommended for better QoR for Design Compiler.
Synopsys even has a great appnote about this called "Coding Guidelines for Datapath Synthesis".
You can find it on solvnet.

Terry
 
  • Like
Reactions: anex16

    anex16

    Points: 2
    Helpful Answer Positive Rating
Thanks Terry. The document is really helpful.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top