Application of GCLK pins Xilinx Spartan 6

Hello!

I have some questions about gclk pins in spartan 6 die. I want to output frequency from fpga to external board. I know that gclk pins is dedicated clock pins and they directly connected to bufg. I tried to synthesis necessary frequency with a help of fpga pll and output it through gclk, but ISE generated error. ISE offered to use ODDR2 component. I applied this suggestion. But if i use such method I can use gpio pins and they will be the same like gclk, if comparison criteria is signal's quality, skew. Am I right? And I assume that GCLK pins can directly attach to global clock net only as inputs.

I know that there are a lot of similar threads in the forum, but definite answer i did not find.

Thank you!

Originally Posted by kirill

ISE offered to use ODDR2 component. I applied this suggestion. But if i use such method I can use gpio pins and they will be the same like gclk, if comparison criteria is signal's quality, skew. Am I right? And I assume that GCLK pins can directly attach to global clock net only as inputs.

Correct. The clock input has to go through a dedicated clock input, through a BUFG. Then you do your pll stuff, the output of which goes again to a global clock net. And then you use the ODDR2 primitive to generate the clock output, which can use any generic output pin.

As for skew, you may want to check out the IODELAY2 primitives, which might be of use to you here...

Hope that answers your questions.

Thanks for your reply, mrflibble!

I try to understand can i use gclk as output and its directly connected to global clock net. If I write in the code : "gclk <= pll_output" ISE generates error. I can write the constraint "PIN "your_instance_name/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;" and error will replaced by warring. But the path of the signal does not route through global clock net all the way, i suppose that when look at fpga editor. I attach two pics, one when gclk work as input and has path delay 0.7 ns, and another when the same gclk pin work as output(with constraint) and has delay 3 ns.

Not quite sure what the problem is?

You want to send the output of the PLL to an output pin, so that you can use that clock signal for some external device right?

Then you can do something like:

Code:

ODDR2  ddr2_as_clock_output_thingy (
   .Q(clock_output),   // 1-bit DDR output data
   .C0(pll_output), // 1-bit clock input
   .C1(~pll_output), // 1-bit clock input
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

And then in the .ucf connect the "clock_output" signal to the IO pin you want.

i know about oddr2) i try to understand if it is true that gclk pin could not work like output directly connected to global clock net.

The answer would be that strictly speaking, no you can't.

Luckily that strict distinction doesn't matter (IMO), since you can still output that clock output from the pll on the gclk pin or any other regular io pin.