Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

two dimensional input/output ports in verilog

Status
Not open for further replies.
mrflibble

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,720
Helped
679
Reputation
1,360
Reaction score
652
Trophy points
1,393
Activity points
19,551
Since this is of use to the fpga programming crowd as well, thought I might as well put it here as well. (original here)

---

Grrrrr, it's 2011 and you still can't pass a simple 2-dimensional input or output to a module in verilog...

Googling didn't really turn up anything , so I put together these quick macros. So far seems to do the trick.

Code: 
`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST)    genvar pk_idx; generate for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin; assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; end; endgenerate

`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC)  genvar unpk_idx; generate for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin; assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; end; endgenerate


module example (
    input  [63:0] pack_4_16_in,
    output [31:0] pack_16_2_out
    );

wire [3:0] in [0:15];
`UNPACK_ARRAY(4,16,in,pack_4_16_in)

wire [15:0] out [0:1];
`PACK_ARRAY(16,2,in,pack_16_2_out)


// useful code goes here

endmodule // example


In a real module of course I put the macro's in a seperate .v file and just `include it.

As a matter of naming convention I use "pack_WIDTH_LEN_original_name" so I can keep track of what the hell it is I packed in there.

Anyways, hope it is of some use to a future verilog victim.
 

two dimensional I/O port or even higher dimension can be easily supported by using SystemVerilog, which is already supported by Design Compiler and Synplify
 

wsong0210 said:
two dimensional I/O port or even higher dimension can be easily supported by using SystemVerilog, which is already supported by Design Compiler and Synplify
Click to expand...

Indeed. But that won't help existing verilog projects...
 
Last edited:

The syntex of SystemVerilog includes all features of Verilog. Therefore, the existing verilog project do not need to change anything. Just change the code where new features in SystemVerilog is needed and then it works.
 

Understood. I didn't really explain all that well what I meant. What I meant was that for an existing project that is already using a certain design flow, it will be more than just a few minutes (or hours) to change it to the new flow.

I would be willing to invest some time in it though, since right now I am flushing time into solving the wrong kind of problems. That being stuff like 2-dimensional ports lacking, etc.

Currently I am using ISE 13.1 for all steps, so synthesis, map, place & route. And Isim 13.1 for simulation.

Suppose I would want to try out SystemVerilog with this as starting point, what would be the best way to evaluate this in your opinion?

If I understand correctly then I'd have to let the synthesis be done by for example Synplify, right? And then feed that to the xilinx tools again for mapping and place & route.

And since Isim doesn't do SystemVerilog AFAIK, I'd need a different simulator as well. What would be a good option? ModelSim? I've used that one in the past before changing to Isim so that should be doable.

Any specific versions that I should be using/avoiding?

This is for a project with a xilinx spartan-6 BTW...
 

Unfortunately ISE, at least to ISE 11, I found the SystemVerilog is not supported yet.
I strongely believe it will be supported in the near future. Maybe you can check the advanced parameters of XST, may be it is already supported?
(If it only shows Verilog 2001, means SystemVerilog is not supported yet)

SystemVerilog is a packet built based on the original Verilog. It add many features to support better test benchs, random test, functional verification which are not for synthesis.
The synthesis tools support only those features which are synthesiszable, including: multi-dimensional ports, wires and regs; multi-dimensional assignment, better generate loops, structured type definition in ports; etc.

ModelSim, AFAIK, is not good at supporting SystemVerilog as Mentor produces another tool dedicated for SystemVerilog support.
The VCS from Synopsys, NC-Simulator from Cadence, support SystemVerilog pefectly. I personally suggest NC-simulator is the best tool.

There is no problem of using SysemVerilog for synthesis; DC, SoC-encounter and Synplify support SystemVerilog.
Once the systemVerilog source code is synthesized, there is no difference with the verilog flow as netlists are in verilog.

The tool flow I use: synplify for source synthesis, ISE for P&R, NC-Simulator for simulation.

---------- Post added at 19:22 ---------- Previous post was at 19:08 ----------

Oh, if you are not going to do RTL level simulation, Isim or Modelsim should have no problem for post-synthesis sim or post-layout, as netlists are in verilog already.
 
Thanks!

As for ISE 13.1, still no SystemVerilog support.

So if I understand correctly I can just use Synplify for synthesis, and this spits out .edif files. Which are then used by map + par from ISE, yes?

As for simulation, I use both RTL and post place & route. But as a first test I could work with just being able to do post-par simulation. One thing about that (and constraints) ... I hope the Synplify tool doesn't mess up the netlist names in new and interesting ways...

And now lets hope synopsys is not too slow with handing out evaluation licenses / giving ftp locations and such. So far I'm waiting for even a download link so I can see if it works under linux. Not much use having a trial license if it doesn't work. :p Looks like they are gone for the weekend...

Oh one other thing, do you happen to have any good links on getting this tool flow to work? That being synplify for synthesis, ISE for P&R, and NC-Simulator for simulation?
 

If you are going to download softwares from symopsys directly and asking for a valid license (buy or evaluation), there will be no problem for you to use them on Linux.
However, I cannot do anything to help you setting up the enviornment as we do have technicans who specialized at this work. Be honst, I just use the tools which are available.

What is certainly sure, synplify is far more efficient then XST. It support complicate constraints with better timing optimizations.
About the name problem, I believe both XST and Synplify may opt out some wires, duplicate wires/regs, and change names. If you use retiming or flatten hierarchy, the names are definitely changed. However, you can use constraints to keep the wires just like what you can do in XST.
Frankly speaking, I dont think it is necessary unless you encountered some unkown bugs. The new name is related to the original name. They are easy to tell.

edif is the right answer. Synplify output edif and use the edif in ISE.

About the good links about the tool flow, I suppose you know how to use synplify and ISE already.
NC-Sim is more command line based instead of GUI, but command lines are far more efficient than GUI.
Look the ncsim.pdf file in /IUS_installation_dir/doc/ncsim/ncsim.pdf
Personally I dont trust any third-party website about how to use a tool. Manual is the best just like the man page of a linux command.

The documents for synplify are also powerful. Synlify is easy to use. You dont need to understand complicated constraints before the first try. But understand the constraints will help you a lot in the future if you are dedicated to FPGA desgn.

---------- Post added at 00:15 ---------- Previous post was at 00:02 ----------

Just a hint,
In NC-Sim, first compile the simprime library files in your ISE vlog dir (supposing a post-layout)
then compile your post-layout verilog netlist (be sure the sdf path is right)
All these two steps use the ncvlog command
use ncelab to link all files together
use ncsim to simulate
If you need GUI, ncsim -gui "the name of your test bench"
 
Thanks for the tips! :)

Download from synopsys is the plan yes. Waiting for confirmation of the trial license request...

It's good to know that the documentation is of good quality. That's not always the case with all products. ;)

Did a bit more reading in the meantime. Adding synplify to the ISE flow looks to be fairly straightforward. And with "But understand the (synplify) constraints" you mean the synthesis options that you can give in the form of a verilog comment?

reg [7:0] counter // some_synplify_directive

those you mean?

The plan is first to get synplicity just taking the place of xst, and see if that works... If yes, add a little actual systemverilog and see if that works. After that I can take a look at the simulation...

About that "In NC-Sim, first compile the simprime library" ... that's with compxlib I take it?
 

the comment in verilog is only directives.
Directives are weak because they are guide for synthesis and may not be undertsand by other tools.
Constraints, something like the ucf files in ISE, but is more powerful in synplify.

I am not sure about what is compxlib, anyway, you need to compile any libraries you need to do post-layout simulation. These libraries may be already compiled in Modelsim if you use the XE version. However, using NC-Sim you need to compile them yourself.
 
Good to know these constraints are more powerful than for ISE.

As for directives not being understood by other tools, that's always the problem isn't it. Either you use the vendor specific options to get the best performance at the expense of less portable code. Or you have 100% tip-top portable code ... at the expense of lower performance.

The compxlib tool is what I used waaay back to compile the simulation libraries for Modelsim.



Looks like it...
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top