Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Assura RCX exits with bad status

Status
Not open for further replies.

psrkforuvlsi

Newbie level 5
Joined
Jul 22, 2009
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
hyderabad
Activity points
1,337
Hi,

I wanna extract C only for my block. I have done rc extraction for a couple of blocks. but this time, assura is quitting with a strange error
=================================
cat <<ENDCAT> sch_cap_ground
VSS
ENDCAT
sch2lay -a -r /design/sysext/dt02/users/sivaram.popuri+dt02+dt02z+4/ver/lvs/integ_blk_siva/integ_blk_siva.gnx -rd /design/sysext/dt02/users/sivaram.popuri+dt02+dt02z+4/ver/lvs/integ_blk_siva/integ_blk_siva.gdx sch_cap_ground lay_cap_ground
*WARNING* at "sch2lay": Unsuccessful translation for VSS in subckt integ_blk_siva
CAP_GROUND=`findCapGround -gfn lay_cap_ground NET`
*ERROR* at "findCapGround": file lay_cap_ground is empty. CAP_GROUND cannot be set. Exiting.

*WARNING* Bad return status from RCX run. 0x100
=====================================================================

Has anyone seen the similar error before. I'm browsing through cadence sites as well as googling... But I'm unable to trace this lay_cap_ground.

Thanks,
Siva
 

I opened up the lay_cap_ground file and I cud see the file is empty. I appended lay_cap_ground file with vss, added a vss pin to the layout& schematic which has resolved the issue.
 

I opened up the lay_cap_ground file and I cud see the file is empty. I appended lay_cap_ground file with vss, added a vss pin to the layout& schematic which has resolved the issue.


hi,siva
actually I have faced the same problem that u have described here,and I have tried to solve this in that way but the problem is I could not find that lay_cap_ground file. so it would be really helpful if u can tell me where I will get that file.

thanks
amit
 

@AMITH,

In your RCX run window, you can find the run details tab.In the run details tab, you can find run directory and both sch_cap_ground as well as lay_cap_ground would be created by Assura. If you cant find, you can create it by yourself.

Thanks,
Siva

hi,siva
actually I have faced the same problem that u have described here,and I have tried to solve this in that way but the problem is I could not find that lay_cap_ground file. so it would be really helpful if u can tell me where I will get that file.

thanks
amit
 

I just had the same problem. But i solved it in another way. I set the Space Name in QRC->Extraction from Schematic Names to Layout Names. Then it works.

- - - Updated - - -

I tried your solution method. It doesn't work in my case. Don't know why. I appended the VSS in lay_cap_ground, saved it and simulated the QRC again, but it failed. Then i opened the lay_cap_ground and found that it is empty again.
 

You need a Ref_Node, in physics we call that a reference-ground-plane, for the E-fields that gets decoupled to this node.
There are few small , however important things, once understood and taken care of - rest is very easy.

From layout perspective the substrate - is the reference node.

If you are using Net-Name-Space "Layout" - use the node name - of your omnipresent substrate layer.
How to know? - what node-name did my substrate get?
- Use LVS probing
- you can check extracted Layout-netlist - and see what is the ground netname.

If you are using Schematic as input net name space, use schematic netname.

Don't mix.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top