process variation aware VLSI design

Hi, i am a new PhD student, and topic of my study is "PVT variation aware VLSI design". As i am very new to this field, so i need guidance in this regard. Please answer my following questions
1) To model process variations for digital VLSI design at architecture level which tools are used (e.g HSPICE, SYNOPSYS)?
2) Which is the latest technology to work with (90nm, 45nm or other) ?
Any books/articles or research papers on this topic would be highly appreciated.

Hello-

I have been working in a similar area. All of my design has been in 65 nm CMOS. However, we will soon be trying the 45nm. The latest technologies are near 20nm but you need to look at manufactures to see what is coming next (e.g. ST microelectronics).

1. I have done transistor or circuit level simulations using cadence. The manufacture provides all of the global and local variation information. At a higher level you may be able to use synopsys.

2. One newer article does a great job of explaining PVT is here:
Bull, D.; Das, S.; Shivashankar, K.; Dasika, G.S.; Flautner, K.; Blaauw, D.; , "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation," Solid-State Circuits, IEEE Journal of , vol.46, no.1, pp.18-31, Jan. 2011
doi: 10.1109/JSSC.2010.2079410
URL: IEEE Xplore - Sign In

good luck,
analogLow