Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VHDL: clock events and concurrent statements

Status
Not open for further replies.
K

KaluzaKlein

Junior Member level 1
Joined
Dec 28, 2010
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,408
Can concurrent statements be synchronous?
I have a when-else statement like the following and I want to make it execute at the rising edge of the clock:

sig1 <= '1' when (sig2 = '1') else
'0'

can it be done without a process?
 

No, it can't. Concurrent statement can only produce latch, not a flip-flop.
 
Actually they can. You have to have 1 signal creating the async logic, and another signal to register it. You can do the following to produce a flip flip:

d <= '1' when (sig2 = '1') else '0';
q <= d when rising_edge(clk); --creates a register.
 
TrickyDicky said:
Actually they can. You have to have 1 signal creating the async logic, and another signal to register it. You can do the following to produce a flip flip:

d <= '1' when (sig2 = '1') else '0';
q <= d when rising_edge(clk); --creates a register.
Click to expand...
Wow, this is so simple! I thought it won't synthesise, didn't even try...
 

Its fine for very simple things like my small example, but it can quickly get a bit unreadable. Best stick to processes and well written code.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top