Thread: Leakage power reduction

Hi Kumar,

we can perform the following methods for Power opt

Supply voltage reduction
clock gating(dynamic power reduction)
Multi Vt
Mutivoltage design(using level shifter cells)
Power switching(using isolation cells and retention registers)
DVFS(dynamic voltage and frequency scaling)


cheers,

hi..
if u reducing Vt means.. the leakage power will increase.. so if u want to reduce leakage power u have to go for high Vt cells or MTCMOS, variable Vt CMOS, multi VDD design or power gating methods.. basically in high freq design dynamic power dissipation will be more n leakage will be less... there will be lot of tradeoffs b/w leakage/dynamic power, freq and no of Vdd's....