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    Leakage power reduction

    What are all the methods you use during the leakage power optimization other than Vt swapping?

    •   Alt1st April 2011, 15:21

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    Re: Leakage power reduction

    Hi Kumar,

    we can perform the following methods for Power opt

    Supply voltage reduction
    clock gating(dynamic power reduction)
    Multi Vt
    Mutivoltage design(using level shifter cells)
    Power switching(using isolation cells and retention registers)
    DVFS(dynamic voltage and frequency scaling)


    cheers,
    The Seven Deadly Sins



    •   Alt1st April 2011, 17:14

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    Re: Leakage power reduction

    Hi Pavan, Thanks a lot. I'm specifically looking for the leakage power optimization methods.



    •   Alt1st April 2011, 18:30

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    Re: Leakage power reduction

    Methods for leakage power optimization are
    1. Reducing Threshold Voltage(Vt)
    2. source biasing
    3. body biasing



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    Re: Leakage power reduction

    hi..
    if u reducing Vt means.. the leakage power will increase.. so if u want to reduce leakage power u have to go for high Vt cells or MTCMOS, variable Vt CMOS, multi VDD design or power gating methods.. basically in high freq design dynamic power dissipation will be more n leakage will be less... there will be lot of tradeoffs b/w leakage/dynamic power, freq and no of Vdd's....
    Last edited by dineshrayar; 2nd April 2011 at 06:50. Reason: adding some points...



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    Re: Leakage power reduction

    presently I use HVT cells to reduce the leakage power. Does std cell library contains the MTCMOS cells also?



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