rjin
Newbie level 2
+crc in usb
Hi, i'm new to VHDL and currently working on designing a USB SIE controller but i'm stuck on the CRC part. I've tried generating it using the bit serial approach but didnt quite get the results ( i used examples from the "CRC in USB" whitepaper).Could anyone pls point out my errors, thanks.
Btw there's another parallel approach which is usually used for hardware acceleration, could anyone pls enlighten me on how it functions? Thanks
Hi, i'm new to VHDL and currently working on designing a USB SIE controller but i'm stuck on the CRC part. I've tried generating it using the bit serial approach but didnt quite get the results ( i used examples from the "CRC in USB" whitepaper).Could anyone pls point out my errors, thanks.
Code:
library ieee;
use ieee.std_logic_1164.all;
entity crc5 is
port( clk: in std_logic;
rst: in std_logic;
stuffed_data: in std_logic;
out_crc5: out std_logic_vector(4 downto 0));
end crc5;
architecture crc5 of crc5 is
signal crc5_state : std_logic_vector(4 downto 0);
begin
process
variable shift_register : std_logic_vector(4 downto 0);
begin
WAIT UNTIL clk'EVENT AND clk = '1';
crc5_state <= shift_register;
out_crc5 <= NOT crc5_state;
if rst = '1' then
shift_register := "11111";
out_crc5 <= "11111";
ELSE
crc5_state(4) <= crc5_state(3);
crc5_state(3) <= crc5_state(2);
crc5_state(2) <= crc5_state(1)xor stuffed_data xor crc5_state(4);
crc5_state(1) <= crc5_state(0);
crc5_state(0) <= stuffed_data xor crc5_state(4);
shift_register := crc5_state;
end if;
end process;
end crc5;Btw there's another parallel approach which is usually used for hardware acceleration, could anyone pls enlighten me on how it functions? Thanks
