Lowest jitter relaxation oscillator

Hi all, first post here - hope you might be able to help!

I need to design a 10MHz board level oscillator which has a 1/C frequency dependence (i.e. the 'C' will vary). I'm thinking that a relaxation oscillator would do the trick as its output f is proportional to 1/RC. However, the most important performance spec for this application is the output jitter, and I'm wondering a) whether a relaxation oscillator is 'good' for jitter and b) what would be the lowest jitter implementation if it was? I'm thinking perhaps a really fast comparator would be best, but then maybe a low noise, high frequency opamp might also be good? The output will be going into the inputs of a phase detector, and to confirm this is a PCB design with off the shelf parts.

Any suggestions?

The lower your edge rate, the greater the multiplication of
voltage-domain noise to time-domain noise. The comparator
itself wants to be fast and have a very narrow linear input
window (i.e. fast at low overdrive). But nonetheless, look
at what P-P noise amplitude you can get on the timing ramp
and how long the ramp dV/dt takes to pull through that
span, and there's your dt (jitter) P-P. Assuming everything
else in the lineup contributes none at all.

A higher frequency oscillator and digital division will lessen
the jitter a fair bit. But getting past 100MHz with glue
logic may be a stretch. At least with anything that doesn't
burn a whole mess of power.

Yes that makes perfect sense. I wonder how a simple schmit trigger oscillator compares but I guess it must be worse since your thresholds there will have pretty poor power supply rejection compared to the differential input of a comparator.

So make it run as fast as possible and divide it down - but what's the effect of the dividers, assuming one uses D types?

How about ditch the relaxation approach and go for a Wien or phase shift 'analogue' oscillator? I suppose that may be bad news as if you want it to drive logic then you are doing a pretty horrible multiplication of the slow voltage noise slopes into time domain jitter..?