richardhit
Newbie level 1
Hi All,
I am designing a 10-bit pipelined ADC with an on-chip sample and hold amplifier that operate at 40MHz with a power supply of 3V.
I don't kown the relationship between INL and the output residue of each stage.
For example, when I simulate the pipelined adc, which is differential input. The positive input is 2V, and the negative one is 1V, while the common mode voltage is 1.5V. The resolution of each stage is 2.5bit.
Assumed the requirement of INL is +-0.3LSB,
how does the output residue of each stage meet the requirement of INL?
Please forgive my ignorance.
Thanks.
Best regards.
I am designing a 10-bit pipelined ADC with an on-chip sample and hold amplifier that operate at 40MHz with a power supply of 3V.
I don't kown the relationship between INL and the output residue of each stage.
For example, when I simulate the pipelined adc, which is differential input. The positive input is 2V, and the negative one is 1V, while the common mode voltage is 1.5V. The resolution of each stage is 2.5bit.
Assumed the requirement of INL is +-0.3LSB,
how does the output residue of each stage meet the requirement of INL?
Please forgive my ignorance.
Thanks.
Best regards.