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[SOLVED] Error in Verilog code

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dpaul81

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HI all,

I am very new to Verilog and am getting the following error!
"A net is not a legal lvalue in this context"
The places where I am getting the errors have been marked in the code given below:

`timescale 1 ns / 1 ns

module up_down_counter (clk, n_reset, up_down, inp_data, cnt_out);

// Port Names
input clk, n_reset;
input [1:0] up_down;
input [7:0] inp_data;
output [7:0] cnt_out;

// Int. Variables
reg [7:0] count;

// Main Code
always @(posedge clk)

begin

if (n_reset) // active high reset
begin
cnt_out <= 8'b0; <-- ERR
end

else
begin
if (up_down == 2'b00) // do nothing
begin
cnt_out <= count; <-- ERR
end
else if (up_down == 2'b01) // count up
begin
cnt_out <= count + 1; <-- ERR
end
else if (up_down == 2'b10) // count down
begin
cnt_out <= count - 1; <-- ERR
end
else
begin // load data
count <= inp_data;
cnt_out <= count ; <-- ERR
end
end


end

endmodule

--------------------------------

Please help!!

Thanks in advance,
dpaul
 

The error means, that count_out must be of the reg type.
 

dpaul81 said:
HI all,

I am very new to Verilog and am getting the following error!
"A net is not a legal lvalue in this context"
The places where I am getting the errors have been marked in the code given below:

`timescale 1 ns / 1 ns

module up_down_counter (clk, n_reset, up_down, inp_data, cnt_out);

// Port Names
input clk, n_reset;
input [1:0] up_down;
input [7:0] inp_data;
output [7:0] cnt_out;

// Int. Variables
reg [7:0] count;

// Main Code
always @(posedge clk)

begin

if (n_reset) // active high reset
begin
cnt_out <= 8'b0; <-- ERR
end

else
begin
if (up_down == 2'b00) // do nothing
begin
cnt_out <= count; <-- ERR
end
else if (up_down == 2'b01) // count up
begin
cnt_out <= count + 1; <-- ERR
end
else if (up_down == 2'b10) // count down
begin
cnt_out <= count - 1; <-- ERR
end
else
begin // load data
count <= inp_data;
cnt_out <= count ; <-- ERR
end
end


end

endmodule

--------------------------------

Please help!!

Thanks in advance,
dpaul
Click to expand...

just simply change

one line

output reg [7:0] cnt_out;
 
Thanks to all those who have replied!

@ above : If I have understood properly, your suggestion means that the output port has to be declared as a register 'cnt_out'. Now why would I do that? Is there any other way to solve the issue?

What I really want to do is to work with an internal 8 bit variable/reg and do all operations on that. Later I want assign that reg to the output port 'cnt_out'! Any suggestions how to do that?

p.s. - I was with VHDL with for 2 yrs, now I need to shift to Verilog, and I am really feeling the hard difference. :(
 
Last edited:

Now why would I do that? Is there any other way to solve the issue?
Click to expand...
It's simply required. In VHDL, a register is generated automatically, you don't have the option to specify different signal types.

If you prefer learning Verilog by try and error, which is basically possible, then you should try to get a sense for the compiler errors and find out what they mean. Having a Verilog text book at hand won't be a bad idea. You'll realize, that the differences between VHDL and Verilog are limited to a few language constructs and can be remembered easily.
 
ok...then I'll accept it as a rule that output ports that deliver data needs to be declared as an internal variable of type register.

I have a Verilog book at hand, but I am running against time (can't read through the basic chapters now)! Need to pick up Verilog as fast as possible and then deliver some task! That's why thought of posting the error in this forum instead of breaking my head & losing time over the error!
And the VHDL knowledge in my head, makes things more difficult! :-(
 

dpaul81 said:
ok...then I'll accept it as a rule that output ports that deliver
data needs to be declared as an internal variable of type register.(
Click to expand...

not exactly,
simply saying if you assign a value to an object inside
'always' block, the object has to be declared as 'reg'
otherwise as 'wire' which is a default type;

execpt the wrong declaration your code will not work,
instead of increase/decrease the 'cnt' value
you assign to the port 'count-1'/'count+1' what probably
is not your intention;

the code should looks something like this:
Code: 
//....//
output [7:0] cnt_out;

 reg [7:0] cnt;

always @(posedge clk)
  cnt <= cnt + 1;
 //....//

end //always

 assign cnt_out = cnt;

////   or   ////

//...//
output [7:0] reg cnt_out;


always @(posedge clk)
  cnt_out <= cnt_out + 1;
 //....//

end //always
---
have fun
 
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    dpaul81

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not exactly,
simply saying if you assign a value to an object inside
'always' block, the object has to be declared as 'reg'
otherwise as 'wire' which is a default type;
Click to expand...
Yes. If you take a look at the gate level synthesis result, you'll notice that the same happens in a VHDL coded design. The edge sensitive process causes register inference. The difference is that Verilog requires the register to be explicitely declared.
 

dpaul81 said:
HI all,

I am very new to Verilog and am getting the following error!
"A net is not a legal lvalue in this context"
The places where I am getting the errors have been marked in the code given below:

`timescale 1 ns / 1 ns

module up_down_counter (clk, n_reset, up_down, inp_data, cnt_out);

// Port Names
input clk, n_reset;
input [1:0] up_down;
input [7:0] inp_data;
output [7:0] cnt_out;

// Int. Variables
reg [7:0] count;

// Main Code
always @(posedge clk)

begin

if (n_reset) // active high reset
begin
cnt_out <= 8'b0; <-- ERR
end

else
begin
if (up_down == 2'b00) // do nothing
begin
cnt_out <= count; <-- ERR
end
else if (up_down == 2'b01) // count up
begin
cnt_out <= count + 1; <-- ERR
end
else if (up_down == 2'b10) // count down
begin
cnt_out <= count - 1; <-- ERR
end
else
begin // load data
count <= inp_data;
cnt_out <= count ; <-- ERR
end
end


end

endmodule

--------------------------------

Please help!!

Thanks in advance,
dpaul
Click to expand...

`timescale 1 ns / 1 ns

module up_down_counter (clk, n_reset, up_down, inp_data, cnt_out);

// Port Names
input clk, n_reset;
input [1:0] up_down;
input [7:0] inp_data;
output [7:0] cnt_out;
reg [7:0] cnt_out1;

// Int. Variables
reg [7:0] count;

// Main Code
always @(posedge clk)

begin

if (n_reset) // active high reset
begin
cnt_out1 <= 8'b0; <-- ERR
end

else
begin
if (up_down == 2'b00) // do nothing
begin
cnt_out1 <= count; <-- ERR
end
else if (up_down == 2'b01) // count up
begin
cnt_out1<= count + 1; <-- ERR
end
else if (up_down == 2'b10) // count down
begin
cnt_out1 <= count - 1; <-- ERR
end
else
begin // load data
count <= inp_data;
cnt_out1 <= count ; <-- ERR
end
end

always@(posedge clk)
begin
cnt_out <= cnt_out1;

end

endmodule


so final output will be available after 2 clock cycles due to pipelining...

enjoy....
 
Thanks "j_andr" for pointing out the difference.
 

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