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operating @ high frequency with xilinx cores on virtex 6 FPGA

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Hello;

I want to ask a few questions about performance of FPGA cores at high clock frequency. I'm trying to operate my system at 500 MHz. I will use FFT core, dds core, FIR filter core of xilinx with my system.

I can generate a system with the cores at 500 mhz succesfully on ISE 11.5; but I wonder if FFT, DDS and FIR filters can operate at 500 mhz together and correctly or I should operate these cores at different frequencies.

what kind of problems may occur at high frequencies?

Is there anyone who had an experience about it? Could you suggest me a method about this subject?

Thanks
 

Hi
if you have a complex design, which operating on high frequency , some signals could not have enough time to get from one trigger to another, and such situations could cause metastability or wrong signals on another trigger next clock. Use period constraint to analyze max operating frequency, if after place and route ise shows errors, so your design perhaps will not on such period of clock. If it happend you should manually place components, route some critical paths , use constraints to increase performance of your design, such method requires some experiance from engineer.
 

500MHz is a very high frequency for these things. What are you processing? At 500MHz you are probably going to hit timing problems, and having more than 1 or 2 logic gates between registers will cause timing failures. At these speeds, it becomes a real hands on design.
 

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