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Design SoC using RTL to GDSII Encounter v9.1

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sumi_88

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Hello,
I am doing a project on designing a SoC using RTL to GDSII encounter v9.1.
I am new to this stuff, hence I am planning to start with an 8 bit microsystem.
Could you help me to start with? I was wondering if there is any possibility of
getting verilog and LEF files for the MCU so that i could directly import the design?


Thanks,
Sumi_88
 

Hi,

Lef files for technology and std cells are from the foundry. They will provide you according to the specific technology for example 90 nm.
You also can create the lef files by yourself using Abstract tool generator, but I never try that.

Thanks

-hairo
 

Hi, I did find LEF files for the 25um technology. But now the problem is with the mtarpt fie. It fails to load saying the no failing paths or library missing. I tried making changes to the sdc file,
yet it says the same. Anyone please help!!!
 

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