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Giving input to Spartan 3e FPGA - each row to subsequent posedges of the clock

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dll_fpga

dll_fpga

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hi,
I'm doing an image compression project,i had used matlab to convert the image into a hex file....now i need to load them into fpga .The hex file is as follows(only 8 rows are shown below...)

9f93969795919294
9f93969795919294
a09793939796938e
9e95918e97959193
9e9b958e95939292
9e9d938f9090938f
979a9691938d9192
9e9b958e95939292
..........................likewise.....about 16000 rows....

I need to input 1st row of this file at the first posedge clock...
second row at the second posedge of the clock...and so forth ..........
How can this be done?
Remember it is not for simulation ......but to load them into actual hardware....
 

Re: giving input to FPGA

Then you have two options:

1. Load all the data into a rom, so it is fixed and never changes on the FPGA and just loads it when you power up.
2. Decide how you want to transmit the data from a PC (RS232, 422, Ethernet etc) and implement a controller for that interface.
 

Re: giving input to FPGA

Hello,

You can simply implement an FPGA module that communicate with you design top level, this module will contain the above values hard-coded, and after reset it will start providing the stimuli to your design at every +ive edge, you may cycle if you need or stop, or trigger the stimuli module using an external switch ... there is a lot of possibilities.

Good luck !
 

Re: giving input to FPGA

TrickyDicky said:
Then you have two options:

1. Load all the data into a rom, so it is fixed and never changes on the FPGA and just loads it when you power up.
2. Decide how you want to transmit the data from a PC (RS232, 422, Ethernet etc) and implement a controller for that interface.
Click to expand...

hi trickydicky,

My fpga board has a USB as well RS232 .....Can you Explain how can the controller be designed?
Can you also mention all the possible alternatives....

---------- Post added at 14:25 ---------- Previous post was at 14:20 ----------
shnain said:
Hello,

You can simply implement an FPGA module that communicate with you design top level, this module will contain the above values hard-coded, and after reset it will start providing the stimuli to your design at every +ive edge, you may cycle if you need or stop, or trigger the stimuli module using an external switch ... there is a lot of possibilities.

Good luck !
Click to expand...

But the file cannot be accommodated in a ROM as each Row of the file is 64bits and there are 1600 such rows.....
 

Re: giving input to FPGA

It will be up to you to find the specs for the protocol you want to use to transfer the data and create a controller. You may be able to find one on opencores.org. Otherwise you'll have to code it yourself. My understanding is USB is a really difficult protocol to implement on an FPGA.

It will depend on your board what options you have regarding transfer mechanisms.
 

Re: giving input to FPGA

What FPGA/Board are you using ?
 

Re: giving input to FPGA

TrickyDicky said:
It will be up to you to find the specs for the protocol you want to use to transfer the data and create a controller. You may be able to find one on opencores.org. Otherwise you'll have to code it yourself. My understanding is USB is a really difficult protocol to implement on an FPGA.

It will depend on your board what options you have regarding transfer mechanisms.
Click to expand...

Is there a possibility for me to use chipscope for the same....so that chipscope would communicate with my design and provide the inputs...
Is that possible....
(around 1600 rows of data (each row is 64 bits) need to be transferred to the design...)

or does Xilinx coregen's can help me?....

---------- Post added at 15:57 ---------- Previous post was at 15:21 ----------
shnain said:
What FPGA/Board are you using ?
Click to expand...

spartan 3e 16000
 

Re: giving input to FPGA

dll_fpga said:
Is there a possibility for me to use chipscope for the same....so that chipscope would communicate with my design and provide the inputs...
Is that possible....
(around 1600 rows of data (each row is 64 bits) need to be transferred to the design...)

or does Xilinx coregen's can help me?....

---------- Post added at 15:57 ---------- Previous post was at 15:21 ----------



spartan 3e 16000
Click to expand...

CHipscope is used for verification of the design.it is not used for inputting data into the device.However,ROM or lut is the best method.Just creat a lut wherein you store the values and call the values whenever required.
 

Re: giving input to FPGA

TrickyDicky said:
It will be up to you to find the specs for the protocol you want to use to transfer the data and create a controller. You may be able to find one on opencores.org. Otherwise you'll have to code it yourself. My understanding is USB is a really difficult protocol to implement on an FPGA.

It will depend on your board what options you have regarding transfer mechanisms.
Click to expand...

It will also depend on the refresh rate of the image. This will dictate the transfer rate.
don't forget to implement a FIFO because you have clock domain crossing issues.

Regards
 

Re: giving input to FPGA

Tan said:
CHipscope is used for verification of the design.it is not used for inputting data into the device.However,ROM or lut is the best method.Just creat a lut wherein you store the values and call the values whenever required.
Click to expand...

my data is about 64bits*1600 .....is it possible to store that much values in a rom?

any other alternatives?

---------- Post added at 16:21 ---------- Previous post was at 16:18 ----------
lucbra said:
It will also depend on the refresh rate of the image. This will dictate the transfer rate.
don't forget to implement a FIFO because you have clock domain crossing issues.

Regards
Click to expand...

Suppose if i'm using a USB core to communicate with fpga...then should i be able to send the text file to FPGA as we transfer data to a pendrive ...?or does it require additional softwares?
 

Re: giving input to FPGA

you will need to implement a ROM with 2048 addresses (11 lines) and 64bit wide bus.

Like TrickyDicky wrote, USB is not easy to implement, but it is feasable. If you understand the details of the USB core, it will be quite easy to feed the data as input for your compression project.
 

Re: giving input to FPGA

lucbra said:
you will need to implement a ROM with 2048 addresses (11 lines) and 64bit wide bus.

Like TrickyDicky wrote, USB is not easy to implement, but it is feasable. If you understand the details of the USB core, it will be quite easy to feed the data as input for your compression project.
Click to expand...

suppose if i'm adding a USB core to my design ......how can i send the text file to the core?does it require additional softwares ?or would it be possible to send data from windows directly as we send data to a pendrive(flash drives)?
 

Re: giving input to FPGA

you wont be sending the text file as a text file, you should send it as raw data. so you'll need some software to covert the text to data before transmission.
 

Re: giving input to FPGA

Assuming the data out from the USB core is 8bit wide:
you will need to re-arrange this 8bit in a data packet that fits your requirement (64bit wide). This means that your USB data needs to be clocked out from the USB core at a 8x faster rate than the processing clock rate.

2nd issue you will have to deal with:
How will you determine the start of packet? Assuming that you included a 'start of frame' character in the image transfer, you might be able to synchronize with the data stored on the pendrive.

Like I wrote before, study the communication protocol that you want to implement, and a lot of your questions will be answered.
 

Re: giving input to FPGA

TrickyDicky said:
you wont be sending the text file as a text file, you should send it as raw data. so you'll need some software to covert the text to data before transmission.
Click to expand...

If i could get vertex FPGA ...can the problem be simplified?(transferring data from PC)
what are the possible alternatives that i would get there to simplify my task...?
 

Re: giving input to FPGA

no. no FPGAs come with specific transport protocols implemented already. thats down to you.
 

Re: giving input to FPGA

TrickyDicky said:
no. no FPGAs come with specific transport protocols implemented already. thats down to you.
Click to expand...

IF the transfer mode is PCI ,then could i use Xilinx coregen's to generate pci core..... to simplify my work....is that possible?
 

Re: giving input to FPGA

Yes, but you probably wouldnt have to get a virtex for that.
You still have to learn how the PCI interface works, but this will usually be a simple address/data system.
 

Re: giving input to FPGA

TrickyDicky said:
Yes, but you probably wouldnt have to get a virtex for that.
You still have to learn how the PCI interface works, but this will usually be a simple address/data system.
Click to expand...

ok...In this case too... i would need to use a software to change my text file to RAW data know?
so first of all let me study PCI. ...should i refer any additional document's other than PCI bus protocol to accomplish this task?
Can you specify the name of any good text book for PCI?
 

I did something similar, we had to test a large design which consumed
almost all memory of stratix3 fpga, we had stimuli vectors generated
by Matlab in a file;
input data were loaded by a programming cable to an editable rom;
I believe a similar approach is possible with xilinx software/device;

a tcl script repeated the steps below until end of input file:
- stops system clock,
- reads first 1K input vectors from an input hex file,
- loads them to a small input rom,
- enables system clock, input rom feeds data to the dut,
- dut output stored in an output 1K ram,
- after 1024 clocks system clock is blocked,
- next 1K vectors loaded from a file,
- output ram dumped to an output file
- etc;
-------
have fun
 

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