Question on stripline plane "shorting"

Hello,

I would like to ask a question on stripline trace.

I was reading Stripline - Wikipedia, the free encyclopedia and noted in section "Description", the articled said

To prevent the propagation of unwanted modes, the two ground planes must be shorted together. This is commonly achieved by a row of vias running parallel to the strip on each side.

Click to expand...

What does "shorted together" mean? As far as I know, internal stripline signals are sandwiched by adjacent power planes (GND or different power), and there is nothing like "shorting". How can power and GND planes be shorted together, which incurs large burning current? Is the expression wrong here?

And what does this "row of vias running parallel to the strip" mean?


Thanks,
Bob

---------- Post added at 17:40 ---------- Previous post was at 17:27 ----------



And in a DDR2 routing example as shown in the attached picture, I noticed a ribbon-like band of vias connected to GND, which are in turn connected by microstrip (NOT stripline) tracks surrounding the DDR2. They are more clearly shown in the image than the verbal description here.

What is the purpose of this GND via band? Does it have anything to do with the "shorting two ground planes" concept and the "a row of vias running parallel to the strip on each side" treatment?



Bob

The PCB stackup for stripline must be GND, dielectric, signal, dielectric, GND; three metal layers separated by two layers of dielectric material. The Wikipedia description is telling you to make sure that the two GND planes are both at the same voltage potential, so you'd want to connect them together electrically. This is done by running vias to tie them together. Generally, this is done several trace-widths away from the edge of the signal conductor. Think of it like two rows of fence (vias), running parallel to a sidewalk/path (stripline center conductor).

(Top view, looking down, "through" the PCB)

vias o o o o o o o o o o o o o o o o o o
(gap)
stripline ////////////////////////////////////////////////
(gap)
vias o o o o o o o o o o o o o o o o o o


You'll want to use a lot of vias so that you get the benefit of lower resistance/impedance due to multiple parallel conductors (vias). Spacing < lamda,min/10

The article says nothing about shorting a power plane and ground plane together. As a side note, DO NOT use a power plane for one of your ground planes in a stripline design (that should be obvious from the names).

---------- Post added at 12:06 ---------- Previous post was at 12:00 ----------

bobsun said:

And in a DDR2 routing example as shown in the attached picture, I noticed a ribbon-like band of vias connected to GND, which are in turn connected by microstrip (NOT stripline) tracks surrounding the DDR2. They are more clearly shown in the image than the verbal description here.

What is the purpose of this GND via band? Does it have anything to do with the "shorting two ground planes" concept and the "a row of vias running parallel to the strip on each side" treatment?

Click to expand...

The ring around the outside of the board is a "guard band", used to isolate the signal spaces (inside the DDR chip, and outside).

Any electric fields generated on the DDR chip, trying to go outside of the circuit, will prefer to terminate on the ground ring. This keeps the loop-path short, and keeps them from radiating. Also, any signals generated outside the DDR chip will terminate on the ground ring, and return to their source via the common grounding of the entire assembly. This keeps outside E-fields from terminating on the DDR signal lines, inducing unwanted signals onto them.

One immediate question:



For Inner 3 and Inner 6 in the image:
Inner 3 is sandwiched by GND above and a power plane below.
Inner 6 is sandwiched by a power plane above and GND below.

So from the definition of stripline, are they still striplines?


Bob

A stripline circuit uses a flat strip of metal which is sandwiched between two parallel ground planes -from Wikipedia.

It means that it is better if you can connect 2 parallel ground plane using lots of via. multi layer pcb usually have multiple ground plane. In case of 4 or 6 layer pcb that only have single ground plane, it is still better to connect the ground signals from top/bottom layer (copper pour) to the GND plane to achieve this.

-KAK

bobsun said:

One immediate question:

For Inner 3 and Inner 6 in the image:
Inner 3 is sandwiched by GND above and a power plane below.
Inner 6 is sandwiched by a power plane above and GND below.

So from the definition of stripline, are they still striplines?


Bob

Click to expand...

By looking at the PCB stackup, I'd doubt these are stripline layers. This sounds more like simple signal routing (low frequency, relatively speaking) for logic signals and control voltages.

Stripline is a defined-impedance transmission line structure constructed by using a conductor on one layer, bounded by ground planes on either side. They are typically used when transporting RF & microwave signals around a circuit board. Most of these systems require a transmission line characteristic impedance (think 50 or 75 ohm coax cable). The impedance is determined by the dimensions of the stripline architecture, and dielectric constant of the bounding materials.

For more on stripline, start here: **broken link removed**

Have a look around these sites, probably better source of info than wikki on signals etc.
beTheSignal.com
**broken link removed**
Speeding Edge consultants specialize in high-speed PCB and system design disciplines

Dear enjunear,

www.analog.com/static/imported-files/tutorials/MT-094.pdf

I found on this article at page 2 that

Note that the figures below use the term "ground plane". It should be understood that this plane is in fact a large area, low impedance reference plane. In practice it may actually be either a ground plane or a power plane, both of which are assumed to be at zero ac potential.

Click to expand...

It sounds reasonable to me and agrees with most board stackup I have met.

Bob

---------- Post added at 09:55 ---------- Previous post was at 09:49 ----------

Dear marce,

Thanks for these links, I will study them carefully.

Bob

bobsun said:

Dear enjunear,

www.analog.com/static/imported-files/tutorials/MT-094.pdf

I found on this article at page 2 that



It sounds reasonable to me and agrees with most board stackup I have met.

Bob

---------- Post added at 09:55 ---------- Previous post was at 09:49 ----------

Dear marce,

Thanks for these links, I will study them carefully.

Bob

Click to expand...

Call me picky, but I'm not a fan of running RF return currents over my DC power supply plane (connected to a generally noisy power supply circuit). In my place of business, we have lots of high-sensitivity receivers and tough EMI/EMC requirements, so I don't take those kind of chances. In a less stringent environment for noise susceptibility, I think you would be fine.

What is the range of your RF circuits? Exceeding 1G, or more? Could you give me a close number?

I am primarily concerning DDR2 memory interfacing with DSP processors, and the frequency is below 600MHz. According to your definition/experience, is this too high so that power supply plane should be avoided, or low enough such that using power supply plane as return path is fine?


Bob

bobsun said:

What is the range of your RF circuits? Exceeding 1G, or more? Could you give me a close number?

I am primarily concerning DDR2 memory interfacing with DSP processors, and the frequency is below 600MHz. According to your definition/experience, is this too high so that power supply plane should be avoided, or low enough such that using power supply plane as return path is fine?


Bob

Click to expand...

I have worked from HF to K-band, mostly 2-512 MHz, 900-1300 MHz and around 20 GHz, at varying power levels from single watts to a few hundred (RF power amplifiers). The problem I could run into is a big power supply capable of supplying many amps to power the PA can induce a LOT of noise on the power plane, and I don't want any inner RF transport layers (stripline) exposed to that kind of noise... especially any signals that might be coming from the antenna, and going into the receiver, or going back as part of a feedback loop to control output power or gain.

In your situation, the amount of noise on your power plane should be relatively low. Also, you aren't dealing with a receiver that needs to be capable to receiving signals very near the noise floor. The issue of noise contamination of the signal on your stripline is somewhat moot, since your signal levels should be well-above the noise level.

What's interesting is that in DDR2 modules, the address/command/control signals are referenced to the VDDIO plane, not GND.

Another good reference, ddr2

http://www.cdnusers.org/community/allegro/Resources/kits_designin/memory/stp_cdnlivesv2007_ddr3.pdf

Dear Marce,

This document is very pertinent and helped a lot, thanks very much.


Bob

---------- Post added at 18:21 ---------- Previous post was at 18:20 ----------

Dear enjunear,

I still need to study these signal integrity concepts. Thanks very much for the answer.

Bob

---------- Post added at 18:32 ---------- Previous post was at 18:21 ----------

allanvv said:

What's interesting is that in DDR2 modules, the address/command/control signals are referenced to the VDDIO plane, not GND.

Click to expand...

Why do you put VDDIO and GND together? Do you meant to say "VDDIO", not "1V8"?

Bob