[SOLVED] Analog IC layout problem in UMC_18_CMOS techfile

I am facing a problem while doing a simple layout of two RNNPO_RF resistors. It is showing 'gnd' in incomplete nets. I don't know how to connect the ground to the particular substrate of this resistor as it is showing in the images:


The Circuit:




The full layout:



showing the incomplete nets:





How do I connect the incomplete net...

At first the middle node of the resistors should be connected to the substrate line (usually sub! or whatever name you want if in your case you want to avoid global names) and NOT directly to VSS (yours gnd).
Check your tech manual for more details for how to implement the connection between sub! and VSS.In most cases (maybe all) we place a subc in schematic that models this connection and this also comes in layout after the respective update from assura.Do it and if the problem persists i will assist you further.

I am not familiar with the term 'substrate line', it will be greatly helpful if you explain it.
I am currently using IC5141 version of Cadence.

I think you should simply connect ntap on nwell (if resistors lies on nwell) / ptap of psub (if resistors doesn't lies on nwell) to gnd. In each technology I worked with it was a scheme of substrate connection in layout for resistors.

jimito13 said:

At first the middle node of the resistors should be connected to the substrate line (usually sub! or whatever name you want if in your case you want to avoid global names) and NOT directly to VSS (yours gnd).
Check your tech manual for more details for how to implement the connection between sub! and VSS.In most cases (maybe all) we place a subc in schematic that models this connection and this also comes in layout after the respective update from assura.Do it and if the problem persists i will assist you further.

Click to expand...

Hi jimito13
there is no subc device in UMC18, subc is common in IBM RF processes but I have not seen it elsewhere. In this (UMC) case connecting VSS to substrate is perfectly ok, unless special noise isolation is required.

Hi Deepon,
RNNPO is a n-implanted poly res on p-substrate so you need contacts implanted with p to contact substrate
RNPPO is a p-implanted poly res on nwell so you need a n-implanted contact to connect the third terminal of this device

I tried with implanting bith M1_NDIFF/M1_Nwell/M1_PDIFF, as you can see from the post, it is still showing incomplete nets...

dgnani said:

Hi jimito13
there is no subc device in UMC18, subc is common in IBM RF processes but I have not seen it elsewhere. In this (UMC) case connecting VSS to substrate is perfectly ok, unless special noise isolation is required.

Hi Deepon,
RNNPO is a n-implanted poly res on p-substrate so you need contacts implanted with p to contact substrate
RNPPO is a p-implanted poly res on nwell so you need a n-implanted contact to connect the third terminal of this device

Click to expand...

---------- Post added at 14:31 ---------- Previous post was at 13:50 ----------

I tried to connect the third terminal with gnd with M1_NDIFF/M1_PDIFF/M1_NWELL, but still it shows incomplete nets. I have attached snapshots for a deeper insight on the device RNPPO_RF.
The outdie area is of Diff_Cad & inner area of substrate(no mention about it is p type/ntype)

EmilioSergio said:

I think you should simply connect ntap on nwell (if resistors lies on nwell) / ptap of psub (if resistors doesn't lies on nwell) to gnd. In each technology I worked with it was a scheme of substrate connection in layout for resistors.

Click to expand...

---------- Post added at 15:27 ---------- Previous post was at 14:31 ----------

I went onestep further & dis-integrated the device, it contained everything from M1_CAD,M2_CAD,M3_CAD,M4_CAD,DIFF_CAD,SUBSTRATE,SYMBOL layouts.
I am still not able to connect gnd with the body..

Hi Deepon

it looks like your pcell already has B terminals on M1 so it should be sufficient to use metal and no special contacts: how are you checking LVS?

dgnani,

there is no subc device in UMC18, subc is common in IBM RF processes but I have not seen it elsewhere. In this (UMC) case connecting VSS to substrate is perfectly ok, unless special noise isolation is required.

Click to expand...

Ok,i didn't know that.I am working on IBM pdks where subc exists.Thanks for the info although!

dgnani said:

Hi Deepon

it looks like your pcell already has B terminals on M1 so it should be sufficient to use metal and no special contacts: how are you checking LVS?

Click to expand...

dgnani,

I am using Assura LVS...




I took a print screen of the LVS errors for your help,
The 'Psub stamp error Float' means I need to add a PDiff layer & connect it.
But I don't know where to connect as the resistor RNNPO_RF doesn't show whether it is on p-sub or nwell...

hi Deepon

I don't use Assura so I cannot verify it is setup correctly.
If RNNPO is anything like the version available in my PDK it is on psub (just hide everythign but NWELL to verify)
Still it looks like your pcell already provides terminals for B on metal1 so the p contact is already in place.
I would simplifiy your test cell and try to instantiate a single resistor with three terminals, your problem could be
- how you are stamping your pins
- missing vias

dgnani,
As you instructed I simplified the circuit. I have attached an image of the same. But it still shows incomplete gnd connection. I have done several complicated circuits using the same procedure. But for the first time I am using the RNPPO_RF device & facing the problem.
The irony is that:
1. If u check my earlier post regarding the device, u can see that it has m1,m2,m3,m4,m5,m6 & their vias connected in the device level techfile. But I have to again connect all the vias again on the circuit layout for connection of metal1 with the 'plus' terminal.

I don't know what is the problem with this. Isn't there anyone who use assura....

dgnani said:

hi Deepon

I don't use Assura so I cannot verify it is setup correctly.
If RNNPO is anything like the version available in my PDK it is on psub (just hide everythign but NWELL to verify)
Still it looks like your pcell already provides terminals for B on metal1 so the p contact is already in place.
I would simplifiy your test cell and try to instantiate a single resistor with three terminals, your problem could be
- how you are stamping your pins
- missing vias

Click to expand...

---------- Post added at 17:35 ---------- Previous post was at 17:29 ----------

The schematic & Layout:


Incomplete net:

Here is my guess: is the name of the terminal in the layout gnd or gnd! ?
I am not sure how Assura names the nets (using the textDisplay label or the terminal name) but since the label shows 'gnd' while the schematic is using the global gnd! I would look into it

Deepon,

I use Assura all the time. From looking at your simplified test case, it may be that the substrate is not defined and labeled properly. The question is how does the LVS file (not the techfile) define the substrate ? If it just needs a pdiff area with contacts, then you need to have that with whatever label is associated with it. If this is your gnd, then the gnd label needs to be on the pdiff/cont. If you have the body also tied to gnd, then you should only need a metal connection to the pdiff contacts. It is hard to tell not knowing all your layers but does your first circuit have the pdiff and contacts ? Your simplified test case has a gnd connection coming out but where does it connect to the substrate ?

Many LVS files define the substrate to be everywhere where there isn't any well and you generally connect to it using some type of p-diffusion (assuming a p-substrate) by using contacts. The substrate does not have to be connected to anything else physically in your circuit.

If you can clarify what some of the layers are, I may be able to help further.

Hi Deepon and jm

the pcell already has terminals contacting the pwell so there is no other p-diff contact to add.

One gotcha here (I just noticed) is that the two B terminal have to connected together otherwise you get a so-called soft-connect violation (in Calibre jargon): basically you have a stamped piece of metal that connects to substrate then an unstamped piece of metal that connects to the same substrate, this is in most rule files an LVS error

Please try that, re-run Assura and let us know

Dgnani,
I have done as you said, but still there remains incomplete net. I have also renamed the gnd as 'gnd!'.. The problems I am facing is quite odd too.. Inspite of the presence of all the vias of M1,M2,M3,M4,M5,M6(I will add the image), I have to add all the vias again in the circuit level in order to complete the connections of the incomplete nets in 'PLUS' & 'MINUS' terminals...

The LVS errors:

dgnani said:

Hi Deepon and jm

the pcell already has terminals contacting the pwell so there is no other p-diff contact to add.

One gotcha here (I just noticed) is that the two B terminal have to connected together otherwise you get a so-called soft-connect violation (in Calibre jargon): basically you have a stamped piece of metal that connects to substrate then an unstamped piece of metal that connects to the same substrate, this is in most rule files an LVS error

Please try that, re-run Assura and let us know

Click to expand...

---------- Post added at 13:50 ---------- Previous post was at 13:25 ----------

jm,

I have given a detailed analysis of all the elements in the RNNPO_RF resistor.
I have labeled all the elements here..

jm3395 said:

Deepon,

I use Assura all the time. From looking at your simplified test case, it may be that the substrate is not defined and labeled properly. The question is how does the LVS file (not the techfile) define the substrate ? If it just needs a pdiff area with contacts, then you need to have that with whatever label is associated with it. If this is your gnd, then the gnd label needs to be on the pdiff/cont. If you have the body also tied to gnd, then you should only need a metal connection to the pdiff contacts. It is hard to tell not knowing all your layers but does your first circuit have the pdiff and contacts ? Your simplified test case has a gnd connection coming out but where does it connect to the substrate ?

Many LVS files define the substrate to be everywhere where there isn't any well and you generally connect to it using some type of p-diffusion (assuming a p-substrate) by using contacts. The substrate does not have to be connected to anything else physically in your circuit.

If you can clarify what some of the layers are, I may be able to help further.

Click to expand...

Hi Deepon

can you try adding two rectangles of p implant around the metal1 of the B terminal and rerun Assura?

what is the highlight color for net avS157?

OK, so you have a N+ poly resistor (RF version) over p-substrate. The Resistor contains the layers nplus, psymbol, SAB and the plus and minus for the ends. Then there is a red/orange layer I am going to call the bulk (B) which is connected to by poly and metal (and I presume contacts also). The first question I have is - is the red/orange layer part of the substrate layer (light outline) ? If not, then you have two connections you need to make - one is to the bulk (B) node, which you do by the metal/poly contact areas but then you also need to connect to the substrate itself.

Do you know if this is considered a 3 terminal or 4 terminal device ?

3 terminal resistors may only have a well or substrate defined as the third terminal. 4 terminal resistor will have the well or bulk connection and also a substrate connection.

You can look in the Assura LVS file and check for the device extraction statement which should look similar to this:

extractRES( "RRR" rr_body rr_head ("plus" "minus") psub("sub") flagMalformed )

where RRR is the type of resistor (probably rnnpo_rf in your case), rr_body is the name of the layer defined for the body, and rr_head is the name of the layer for the ends.

If you have a 4 terminal device, you will have a 4th layer listed above and then you are generally extracting it using a generic extractDevice command.

By knowing the name of the substrate or bulk layer, you can display it on the layout. You can do this by setting the avParameter "keepData" to "All" in your LVS window (don't forget to click on "use in run"). When you bring up the debug tool, you can use the VLW window and click on the layer for display. I would turn off most or all of the LSW layers first so you can see what displays. This displayed layer is the actual layer that Assura looks for a connection to and it will connect to it using whatever is defined in the geomConnect or geomStamp statements in the LVS file. You can do a search for the substrate or bulk layer to find out that information. This should tell you how Assura wants you to connect to that 3rd or 4th layer.


The issue with the MX_CAD layers may be a separate issue as the incomplete nets is part of the Virtuoso XL functions and the connectivity is controlled by different files than the LVS. I would resolve the LVS issue first and then still see if you have the other issue.

Another thing you can do is to probe the "substrate" layer you have and see if is connected to anything. If it only highlights the "substrate" layer and no other connections, then that is further proof that your substrate is floating and accounts for the psub_float error.

Let me know what you find out and also what the LVS report lists.

jm3395 said:

... Then there is a red/orange layer I am going to call the bulk (B) which is connected to by poly and metal (and I presume contacts also). The first question I have is - is the red/orange layer part of the substrate layer (light outline) ? If not, then you have two connections you need to make - one is to the bulk (B) node, which you do by the metal/poly contact areas but then you also need to connect to the substrate itself....

Click to expand...

The SYMBOL layers are LVS device recognition layers. Poly never ever connects to substrate! You connect to (p)substrate with a (p)diffusion contact!

dgnani -

I would agree that the psymbol layer is probably a recognition layer but it is part of the layer construction of the resistor whether it is a real physical layer or not. It was not clear to me whether the "Symbol" layer was indeed the red/orange layer (the label could have been moved to the wrong layer) and if it is just a marking layer, why draw it as big as it is ? Why not draw it as big as the physical resistor ? If the Symbol layer is the red/orange layer and it is a marking layer, why do you need the poly and metal ? The problem is that without the actual data in front of you, you can assume something incorrectly.

In any case, my assumption was that the red/orange layer is a real physical layer that needs poly/metal contacts and not part of the substrate. If I am incorrect, Deepon's answers will tell me that. I am well aware that you do not connect to a substrate with poly. I did mention in my earlier post that you need pdiff to connect to a p-substrate.

It would be helpful to have Deepon respond and clarify things so we can offer helpful advice.

I am looking at UMC_18 layers and I can tell you that all ?SYMBOL layers are device recognition layers.

You need the poly and metal (and SAB and NPLUS) because those are tapeout layers, necessary for mask preparation.

If you can find an example of physical layers that is not a metal and poly can connect to...

In any case you make a good observation, I had not noticed that there was poly under the B terminals' metal1

This means that those two are dummies (remember this is an RF device) so we still need to connect a p-contact to substrate (should be called something like M1_PDIF).

In summary forget about the previous suggestion of placing p implant rectangles around the B terminal and instead place an M1_PDIF contact (in real RF life you would probably use a guard ring but for now we just want a clean LVS) outside the device perimeter and connect it to gnd! with metal1

This should do the trick