ipunished
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Hello,
Im new to verilog and am learning it myself.. What im trying to do is to create a simple system, a part of it is an irq timer module... its supposed to generate a pulse determined by a parameter and each pulse should last for 4 clock cycles.
here is what i worte (its my first verilog module)
Note: i have no idea how to implement parameter here, i know that its implemented using the leyword parameter in the module header but i dont know how it can be used here for our purpose.
Note: clock is supposed to be 32768 Hz, am i supposed to mention thsi someplace in my code?
Thank you for looking
Im new to verilog and am learning it myself.. What im trying to do is to create a simple system, a part of it is an irq timer module... its supposed to generate a pulse determined by a parameter and each pulse should last for 4 clock cycles.
here is what i worte (its my first verilog module)
Code:
module timer(
input clock,
input reset,
output reg[15:0] irq
);
always@(posedge clock or posedge reset)
begin
if(reset || (irq==16'h8000))
irq<=0;
else
irq<=irq+1;
end
endmoduleNote: i have no idea how to implement parameter here, i know that its implemented using the leyword parameter in the module header but i dont know how it can be used here for our purpose.
Note: clock is supposed to be 32768 Hz, am i supposed to mention thsi someplace in my code?
Thank you for looking
