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two stage OTA design for typical LDO with 0.13um tech

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!! the phoenix law !!

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Hello there !
I know there are some experts here and I think you certainly can help me with this

As the title said, I need help to design a two stage OTA for a typical LDO with 0.13um technology, I am using cadence for simulations,
By typical I mean that LDO stability is achieved by big off chip cap
This is my first trial and i just want a very regular design, however efficient as well

To be specific, I just need specs on the OTA (for the LDO)
So, based on your experience what specs should I follow ?

These are some specs, there might be others i should consider for LDO, If so please tell me, I have also estimated some values but I need someone to confirm

dc (Av)>=60db
unity gain bandwidth (GB)>=3M
input common mode range (Vin(min) and Vin(max))
load capacitance (CL) (from a PMOS pass element with upcox=1.12e-4 and Imax=1mA)
slew rate (SR)
settling time (Ts)
output voltage swing (Vout(max) and Vout(min))
power dissipation (Pdiss)

Moreover, The OTA should have NMOS mirror load (Input transistors for the first stage are PMOS not NMOS), to enhance PSRR

You might need also to know some info about the LDO itself
Output voltage=1.8v
Input voltage>=2
Output current<=1m
PSRR as high as possible

Any other specs like load regulation, line regulation, .. etc might be any reasonable value

Thanks in advance
Any help would be appreciated
 
Last edited:

Thanks erikl, downloaded and currently investigated
It seems very useful, I appreciate your help

I wish if others can also share experience
Thanks Guys
 

@erikl
The gm/Id design methodology is something new for me, the paper does not introduce details though, so can you provide me with another full of some details ? this would be very nice
I already got the big picture but still confused and not able to go for my own design
Thanks
 

In this thread **broken link removed** you can find some links to papers and books about the gm/Id methodology.

The best book using this method, IMHO, is David M. Binkley"Tradeoffs and Optimization in Analog CMOS Design".
 
Last edited by a moderator:
Beside my previous post
If you allowed me, I want to ask some questions about the error amplifier:
My LDO is preceded by a rectifier, the rectifier generates 2v DC from a 13.56meg AC signal, say with ripples 0.1v, My guess that these ripples would be also at 13.56meg and its harmonics, hence My LDO should have a very large PSRR BW, let say 50Meg, am I right ? If so, I guess the DC gain should be minimized, Let say 20-30db ? am I right ?

Another thing, The max current the LDO should supply is very small, typically 1-2mA, So the pass element area is also small, I simulated an ideal circuit and found that its gate capacitance will be less than 1p !! Is this reasonable ? If so, I guess 60deg for the phase margin is fine

Also, ICMR should be something around 1.2v (my BG reference), I guess 1-1.4 is fair enough

what about output swing?

I am still confused about SR and not sure how to relate it to the LDO specs, I guess this parameter is important when Load current steps from max (1mA) to min (0) and related to the transient specs; overshoot and settling time, am I right ?

I also made a Matlab model for the loop, but still not sure what is next to do ? should I vary every stage gain and BW and see the effect on PSRR or stability ?
I think this matlab model might help only in OTA design (not related to the pass element and feedback) choosing optimum value for gain, BW, SR, etc
am I right ?

Thanks sir
 

sorry erikl, i must have put a wring page, anyway let's forgot about this for now,
i think i still do not understand the system enough, that's why i left the tr level design and currently re-investigating the system as a whole

alright, this is a very critical issue, I made a matlab model (with simulink) for the LDO loop, the system has two poles, on dominant p1 at the LDO output and one non dominant p2 at the error amplifier output,
p1=4.5k
p2=500k
the system also has a zero at 500k to compensate p2, this zero comes from the ESR of the output cap
(for simplicity i modeled the error amplifier with only one pole)
The total gain in the loop is 80db from which the amplifier has 60db (and 20db for the pass element)

The input is 2v DC and the reference is 1.2v DC

Now, why does matlab pop up an error when i run the simulation ?
Is the loop unstable ?

To sum up:
The feed forward transfer function is 10*(3.18e-7s+1)/(3.536e-5s+1)
and the feed back transfer function is 1000/(3.18e-7s+1)

Please tell me what is wrong >> I depend on this step to set the specs for each block in the loop, mainly the error amplifier

Thanks
 


hi, according to your description, you are working on the 13.56M RFID, right?
If it's a passive RFID Tag, the regulator is much better than LDO, and 1mA current is quite huge for passive RFID. the psrr and sr depends on your application, you need to consider the load circuits first,
then go back to see the spec of the LDO, there are lots of trade-off in the OTA design.

!! the phoenix law !! said:
Beside my previous post
If you allowed me, I want to ask some questions about the error amplifier:
My LDO is preceded by a rectifier, the rectifier generates 2v DC from a 13.56meg AC signal, say with ripples 0.1v, My guess that these ripples would be also at 13.56meg and its harmonics, hence My LDO should have a very large PSRR BW, let say 50Meg, am I right ? If so, I guess the DC gain should be minimized, Let say 20-30db ? am I right ?

Another thing, The max current the LDO should supply is very small, typically 1-2mA, So the pass element area is also small, I simulated an ideal circuit and found that its gate capacitance will be less than 1p !! Is this reasonable ? If so, I guess 60deg for the phase margin is fine

Also, ICMR should be something around 1.2v (my BG reference), I guess 1-1.4 is fair enough

what about output swing?

I am still confused about SR and not sure how to relate it to the LDO specs, I guess this parameter is important when Load current steps from max (1mA) to min (0) and related to the transient specs; overshoot and settling time, am I right ?

I also made a Matlab model for the loop, but still not sure what is next to do ? should I vary every stage gain and BW and see the effect on PSRR or stability ?
I think this matlab model might help only in OTA design (not related to the pass element and feedback) choosing optimum value for gain, BW, SR, etc
am I right ?

Thanks sir
Click to expand...
 

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