karthik87
Junior Member level 1
Hi i have attached my incomplete Uart Receiver controller code..
My specification.... is Rx clock is 16times faster,i have to sample one data at 16clocks,then the data has to be given to shift register,after i receive stop bit i have to check for frame,overrun and parity errors and then send data to fifo by asserting wr_en and to stop sending the data when full flag is set
pl provide me the logic to write to shiftregister and to send to fifo....and also how to sample the data......and logic to check errors...
pl find the attachment and do the needful
Thanks in advance
My specification.... is Rx clock is 16times faster,i have to sample one data at 16clocks,then the data has to be given to shift register,after i receive stop bit i have to check for frame,overrun and parity errors and then send data to fifo by asserting wr_en and to stop sending the data when full flag is set
pl provide me the logic to write to shiftregister and to send to fifo....and also how to sample the data......and logic to check errors...
pl find the attachment and do the needful
Thanks in advance
