Cascode amplifier Design

Hi all,
I'm trying to design Cascode amplifier(with cascode current mirror as load) in 180nm technology(@vdd=1.8 ) with following specifications
voltage gain 50V/V output swing .6v and ouput impedance of 4Mohm.
I first started by assuming overdrive voltages of all the transistors are same,so with this assumption my Vod is coming to be .3V.With Vod=.3 and Vth=500m my VGS<800m.From my slewrate and powerdissipation constraints I have fixed my bias current.With bias current and VGS(800m) in hand I've calculated the W/L of all the transistors.
With L=180nm I'm getting a gain of 10.2.So I doubled L(and also W in proportion) of all the transistors but my gain isn't getting 4times!! (WHY??)
And with this method I'm getting very low input swing(around 70mV).
How to find ouput resistance of Cascode amplifier?

At first, as you increase the Length of MOS ( assuming the same increase in W), the current capability of Transistor will increase. This means that for the same current, the Overdrive voltage will decrease.

Example L=0.06um ,W=20um , Vds=400 mV, Vgs=700mV==> I=3.45mA

and then for L=0.12um, W=40um and the same voltages ===> I=5.64 mA.

The reason is that for low values of L, the current equation of MOS transistor has a linear relationship with Vgs-Vth for high Over-drive voltages. But as you increase the L, The current equation starts to be more quadratic and therefore will have more current for the same Vod. This is the reason that you get low input swing. ( For the same current Increasing L, will reduce the Vod, as stated above).

About the gain: For the same current, i have found the gmro of the transistor.

Example L=0.06um ,W=20um , Vds=400 mV, Vgs=700mV==> I=3.45mA ==> gmro=4.7

and then for L=0.12um, W=40um, Vds=400 mV, Vgs=605mV ===> I=3.45mA. gmro=8.5


Therefore, the gain of simple transistor will increas by ~2, due to 2 times increase in ro ( lambda will be twice). In the Cascode Amplifier, the output impedance of pmos current mirror is ~gmp*(rop)^2 and therefore you expect it to be 4 times more. But if you don't have the cascode in nmos transistor sizes, the output impedance of the amplifier will be ~ron which means that the gain of your amplifer will increase by 2.

Is the method I'm following correct?
If changing L changes entire device parameters then how do I need to overcome this issue as my method seems to be round about.I haven't got any such phenomenon while designing an OTA .
And how can I increase my input swing??Is it right to keep all the VDS to be same?
Can you explain your methodology!!

Hello all,
Please post your methodology of designing cascode amplifier with these specifications Av=50 and ouput swing =0.6V for a 180nm technode(@Vdd=1.8V)

Hello,

The first thing you should do is to make sure all of your transistors work in the saturation region (i.e. not in linear region or subthreshold or cutoff region).

yeah all my transistors are in saturation but my input swing is very low ,how to enhance it? Impedance seen looking into pmos cascode is 2.9Mohm and NMOS cascode is 2.79Mohm but my circuit output resistance is only 600K,why??

There must be a low resistance path for current at the output node, other than the cascode paths. Can you post your schematic? It's very hard to say without schematic.

drknownothing said:

There must be a low resistance path for current at the output node, other than the cascode paths. Can you post your schematic? It's very hard to say without schematic.

Click to expand...

Here is the schematic of my design

Where is the input stage? Can you post the complete schematic? The one you posted seems to be incomplete.

Input is applied to NMO in the schematic(Single stage amplifier)

I think the problem is your PMOS's W/L is too large. Try decreasing the W of the PMOS to 3um.

---------- Post added at 11:50 ---------- Previous post was at 11:49 ----------

And you may also need to adjust your bias voltages. What is the DC offset of your input voltage?

drknownothing said:

I think the problem is your PMOS's W/L is too large. Try decreasing the W of the PMOS to 3um.

Click to expand...

I've grounded(0V) bottom NMOS and found output resistance of 2.9Mohm similarly with PMOS grounded I got ouput resistance of 2.7Mohm.So my output resistance should be 2.7Mll2.9M approximately equal to 1.5Mohm but it is coming out to be 600K.

drknownothing said:

What is the DC offset of your input voltage?

Click to expand...

I don't know how to find DC offset.

Your way of finding cascode output resistance is incorrect. The realistic value of the PMOS cascode resistance is probably way lower than the NMOS cascode, because of the large W value. That's why I think you should decrease PMOS W and see what happens.

Can you please expalin your methodology to fix W/L ratios and bias voltages of all transistors
And if possible post some schematic for finding output resistance!!!

In principle, under the same Vov, for the same current, (W/L)pmos should be made 2.5x (W/L)nmos. This is because of physics (if you are interested in the details you can read the Gray and Meyer book about it).

BTW, have you tried my suggestion? If so, please let me know the results.

drknownothing said:

In principle, under the same Vov, for the same current, (W/L)pmos should be made 2.5x (W/L)nmos. This is because of physics (if you are interested in the details you can read the Gray and Meyer book about it).

Click to expand...

Me too had same doubt but I've checked thrice why W/L of PMOS aren't 2.5(approx.) times of NMOS(for same Id)!!

Ravinder487 said:

Me too had same doubt but I've checked thrice why W/L of PMOS aren't 2.5(approx.) times of NMOS(for same Id)!!

Click to expand...

You really don't want to let me know the results?

Sorry I couldn't get what you have suggested!
Please clearly mention what do I need to do now

Decrease the W of the two PMOS transistors to 3um, and run the simulation again, check the gain.

If I changed W of PMOS to 3um then they are coming out of saturation!!