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Your clock period is 1000 ns. So it is not possible for you to introduce a 50 ns delay. You need a clock whose time period is less than 50 ns. Then a counter will work.
You can instantiate buffers as much as you need on your signal path in order to achieve the 50 ns (for instance if your technology library has inverters that introduces 2 ns delay then you will have to instantiate 24 or 26 inverters) but the delay will depend on many other factors (nets delay, fan-out ...) hence it's hard to guaranty accuracy so you will have to do many tries before reaching your goal.
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