[SOLVED] What are the possible levels of optimization in a FPGA Design ?

What are Possible Levels of optimizing an FPGA Implementation ....At various stages of the design from synthesis to place and route

I am Using spartan 3 xc3s400

is it better to use synplify premiere than XST?

Well, what possible ways to optimize it have you identified thus far?

Also, maybe you have a specific project in mind to server as an example?

That way we can build on that...

mrflibble said:

Well, what possible ways to optimize it have you identified thus far?

Also, maybe you have a specific project in mind to server as an example?

That way we can build on that...

Click to expand...

trying to implement a RISC cpu ....I had tested xst vs Synplify ...and found some advantage for synplify ....

myself only familiar with Verilog code optimization .

but there is scope for

1.Synthesis Level Optimization

2.Place and route Optimization

Just a couple of semi-random thoughts...

Optimize design to best fit the resources of your target fpga. When designing for spartan-3 (LUT4) you might do things a bit different than for spartan-6 (LUT6).

Use best practices that avoid code that makes your HDL synthesize to something that is larger/slower than necessary. Case in point the idec module in your other thread.

I'd even say optimize the speed of your tools. The more iterations you can do per time unit, the more room for actual creative productivity. More actual work, less waiting for tools to finish compiling... (Know of any good links with regard to speeding up xilinx ISE? I could use some...)

mrflibble said:

Just a couple of semi-random thoughts...

Optimize design to best fit the resources of your target fpga. When designing for spartan-3 (LUT4) you might do things a bit different than for spartan-6 (LUT6).

Use best practices that avoid code that makes your HDL synthesize to something that is larger/slower than necessary. Case in point the idec module in your other thread.

I'd even say optimize the speed of your tools. The more iterations you can do per time unit, the more room for actual creative productivity. More actual work, less waiting for tools to finish compiling... (Know of any good links with regard to speeding up xilinx ISE? I could use some...)

Click to expand...

I got this text ..
Advanced FPGA
Design
Architecture, Implementation,
and Optimization
Steve Kilts

wiley

good coverage on the optimization issues ...

blooz said:

I got this text ..
Advanced FPGA
Design
Architecture, Implementation,
and Optimization
Steve Kilts

wiley

good coverage on the optimization issues ...

Click to expand...

Just took a quick peek. That looks pretty useful, thanks!

I wasn't too impressed. It might be good for an intro to some good design practices, but if you've done a few designs and have read the FPGA tool user guides you'll find it a bit lacking. Especially in terms of any new design considerations for different FPGAs. eg, Virtex-5 FPGA's have seperate synchronous set and reset inputs, while Virtex-6's have a configurable set/reset input. Designs that target V5's might try to order if-else statements to make use of the additional synchronous set, while the same optimizations wouldn't apply to a V6.

Overall, I'd suggest reading though Xilinx's Documentation on ISE and then the FPGA specifics. Altera has a few good doc's as well, as long as you aren't looking for any specific info...

The second biggest gains are nearly always going to be in finding a way to get some part of the design to run slower. Eg, multi-cycle paths and divided-clocks works well for speed optimizations, resource sharing and multi-cycle operations for area optimizations, and divided/gated clocks for power. Converting cycle-by-cycle control to block-processing also allows the control logic to run at a reduced clock, or have additional pipelining. All reduce the performance of some part of the design to the minimum allowed. Then the critical parts can be fine tuned as needed.

The biggest gains in speed will pretty much always come from good pipelining choices.

permute said:

The second biggest gains are nearly always going to be in finding a way to get some part of the design to run slower. Eg, multi-cycle paths and divided-clocks works well for speed optimizations, resource sharing and multi-cycle operations for area optimizations, and divided/gated clocks for power. Converting cycle-by-cycle control to block-processing also allows the control logic to run at a reduced clock, or have additional pipelining. All reduce the performance of some part of the design to the minimum allowed. Then the critical parts can be fine tuned as needed.

The biggest gains in speed will pretty much always come from good pipelining choices.

Click to expand...

Do you have any specific suggestions for reading material dealing with pipelining and multi-cycle operation? Thanks in advance!

blooz said:

trying to implement a RISC cpu ....I had tested xst vs Synplify ...and found some advantage for synplify ....

Click to expand...

I heard its better than XST, but never used it! Please share few quick advantages you noticed.

Jack// ani said:

I heard its better than XST, but never used it! Please share few quick advantages you noticed.

Click to expand...

basically I noticed one thing , resource utilization (LUTs) by Synposis was lesser than that by XST .Currently I am working on it .The design under test was a smaller one - (16 bit ALU) .this week Much bigger design will be tested One of my friend is also switching to synplify premiere from XST ..He is focussing on Jpeg compression and this weekend we are planning to do a benchmark test that Jpeg Compression Design and if there is anything remarkable glad to share the result .
tools are
synplify premiere 9.6 and ISE 12.3 system edition

On the subject of optimization using multi-cycle paths, I found this tutorial:

**broken link removed**

This Course has some material on optimization .explanation is simple and basically it is a simple one.
h**p://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/index.php

Thanks for the tip! Will look into it...