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Verilog constants with parameterized bit width

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fcfusion

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Hello everyone

I have a question regarding constant assigments with parameterized bit width. For example, i want to initialize a register with a constant value 10 . If i wish to use a fixed bit width all I have to do is:

reg [7:0] whatever;

always @(posedge)
begin
whatever <= 8'd10;
end


Now, if I want to define the registers with different bit widths, according to my needs I can simply do:

parameter Nbits = 16;

reg [Nbits-1:0] whatever;

However I do not know how to assign the value to the register, because of the " 8'd " expression.


whatever <= 8'd10; //???????


How can I subsitute this expression for something that can be easily changed through parameters without resulting in synthesis warnings?

Thank you
 

Code: 
parameter Nbits = 16;

reg [Nbits-1:0] whatever;

whatever <= {1'b1, (Nbits-1) {1'b0}}; // something like this
gives you the same as:

Code: 
reg [15:0] whatever;

whatever <= 16'b1000000000000000;
hope that helps

edit

DOH!

I am blind. I didn't see the 'd' there. you are assigning decimal value of 10. Hah, only 10 types of people right? Those that misread binary related questions and those that don't.

Anyway, you could just dispense with the width.

Code: 
whatever <= 10;

or you can pad it with zeroes like this:

Code: 
whatever <= {(Nbits-4) 1'b0, 4'd10};

depending on what you want....
 
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