yx.yang
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Hi, Friends:
I meet a problem when using synopsys power compiler to do Latch based clock gating.
I want aviod cross clock domain data, multi-cycle path data and data from chip input port been used to do clock gating enable calculation. While power compiler do use these signal to do clock gating enable calculation. As there is a lot of these points in my design, I can't find them out manaully one by one.
My question:
a): Is there any power compiler commond or options can achieve this?
b): And how do you deal with these point when you do clock gating? Do you include these points to do clock gating enable calculation?
Thanks.
I meet a problem when using synopsys power compiler to do Latch based clock gating.
I want aviod cross clock domain data, multi-cycle path data and data from chip input port been used to do clock gating enable calculation. While power compiler do use these signal to do clock gating enable calculation. As there is a lot of these points in my design, I can't find them out manaully one by one.
My question:
a): Is there any power compiler commond or options can achieve this?
b): And how do you deal with these point when you do clock gating? Do you include these points to do clock gating enable calculation?
Thanks.