Mismatch responsible transistor in DDA

Hello,

I'm working on Cadence Virtuoso 5.10.41 0.35µm Technology. I'm trying to finish some ASIC design which contains a fully differential DDA amplifier (with Common Mode Feedback and so on). My MonteCarlo analysis (3sigma) reports an Offset of about +-400mV which I consider to be too high (+-10mV required).

How can cadence help me finding the transistors that are more likely to cause the offset? As a first measure, I made the amplifier gates bigger, but didn't seem to make a difference. I think I have many possible sources of offset like: 2 current sources required, CMFB, biasing circuitry of cascoded transistors, resistors... just too many candidates, and I want to do this verification efficiently.

Is there an analysis that shows the offset contribution of each transistor?

Thanks in advance,
Oscar

With 400mV offset, I would rerun that particular MC run and verify circuit functionality. I highly doubt that result was due to offset.

The primary culprit for high offset is the first amplifying state, ie the input pair (You need a high Gm one, and large area of course!). This is followed by having high overdrive current mirrors. If you really want a method, I would think a sensitivity analysis with mismatch as a target might do the work.

Thanks, checkmate,

With a "Process Only" MonteCarlo simulation, the offset is much lower (40µV) and the functionality seems to be fine (Gain, Bandwidth, noise, input range, etc). So that makes me conclude it is a mismatch issue.

Probably you are somehow right about functionality, but I would still blame a mismatch problem. Probably one or more transistors of the biasing stages are going outside saturation region.

For the moment, I will try your hint regarding Sensitivity Analysis with mismatch.

Cheers,
Oscar

If a mismatch causes transistors to operate out of saturation, it only means that
1. Your mismatch is really bad
2. You do not have sufficient enough headroom for a robust design.
I would focus more on the latter, find out where you are operating marginally.

Hi checkmate,

I have tried around a little with your suggestions but it seems the mismatch comes from more than one variable itself. It can be, as you say, that my design operates extremely marginally. Therefore I have tried to follow the next corrections:

1. Make transistors bigger (already big, because I designed for a good noise performance)
2. Raise Vgs voltages (I did it now reducing W/L factor)
3. When splitting transistors, ensure each part is large.
4. Ensure all transistors are in saturation (I did, and I also tried with 6V supply voltage giving a comfortable range for all transistors)
5. Current sources, etc: I'm trying right now with ideal elements biasing.

None of these suggestions did really work. In fact, I re-dimensioned the whole design without caring about the noise performance and it just gets worse. Right now, I'm trying to boost the open-loop gain of the amplifier.

Just in case it can be of help:
1. It's a telescopic amplifier
2. DDA configuration
3. Large input and load transistors
4. The system has an open loop gain of 82dB and is feeded-back for 60dB (which works despite the random mismatch)

Any additional idea?

Cheers,
Oscar