eexuke
Full Member level 4
soc encounter hierarch
Hi,
I am new to this cadence tool. I am confused what is "partition" in it? I have divided my design into several sub-modules in verilog netlist after design compiler's synthesis. Do I still need to do partition in SOC encounter?
Thanks!!
Hi,
I am new to this cadence tool. I am confused what is "partition" in it? I have divided my design into several sub-modules in verilog netlist after design compiler's synthesis. Do I still need to do partition in SOC encounter?
Thanks!!