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How to give clock for the multiplier.

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Kumar_494

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I designed 16-Multiplier in structural level. I didn't give any clock to the multiplier. I am getting the correct output. but when i synthesized in rtl compiler in timing report it is showing unconstraint. And can u please clarify how to prove my multiplier is faster than other?
Thanks in advance
 

Hi Kumar,

Constraint it using a SDC file..ur output will be declared as a reg by default in your HDL code..so u just need to specify your design constraints and timing constraints in a file to your synthesis tool
 
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