simulation xilinx: WARNING:Xst:2040

WARNING:Xst:2040 - Unit MAIN_CONTROtop: 8 multi-source signals are replaced by logic (pull-up yes): Databus<0>, Databus<1>, Databus<2>, Databus<3>, Databus<4>, Databus<5>, Databus<6>, Databus<7>.

WARNING:Xst:2042 - Unit ALU: 8 internal tristates are replaced by logic (pull-up yes): Databus<0>, Databus<1>, Databus<2>, Databus<3>, Databus<4>, Databus<5>, Databus<6>, Databus<7>.

WARNING:Xst:2040 - Unit MAIN_CONTROtop: 8 multi-source signals are replaced by logic (pull-up yes): Databus<0>, Databus<1>, Databus<2>, Databus<3>, Databus<4>, Databus<5>, Databus<6>, Databus<7>.WARNING:Xst:2042 - Unit

ALU: 8 internal tristates are replaced by logic (pull-up yes): Databus<0>, Databus<1>, Databus<2>, Databus<3>, Databus<4>, Databus<5>, Databus<6>, Databus<7>.

Can any1 help me with these ?

Your code describes a data bus to which multiple tri-state blocks are connected. The FPGA doesn't have tri-state internally, so the compiler must transform the design.
It can work, but I think it is better that you do the transformation yourself. Only use tri-state for signals connected to physical pins.