Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

simulation in modelsim.problem with the tool

Status
Not open for further replies.

sns22

Member level 2
Joined
Jan 15, 2011
Messages
46
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Spain
Activity points
1,708
HI;
I am using xilinx for the vhdl code and simulating the same in the modelsim.but is there any version of modelsim for xlinx different than version of modelsim for xlinx?

because i am working with the ip coregen in xilinx which when i simulate using modelsim is not including the coregen libraries while simulating as a result i m not able to use fifo as a part of my code which i have generated using ipcoregen.

the warning i recieve is

Using alternate file: ./wlftjs97rr
# ** Warning: (vsim-3473) Component instance "internal_memory : fifo" is not bound.
# Time: 0 ps Iteration: 0 Region: /tb_rs232top/uut File: files/RS232top.vhd
# ** Warning: (vsim-8684) No drivers exist on out port /tb_rs232top/uut/data_out, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_rs232top/data_out.

if there is any other version of modelsim for xilinx for students which has all the coregen libraries installed in it please let me know?

:-(
 

snehanidhi,

It looks like you need to include the library where your fifo is compiled. Or, you failed to compile the fifo.

So, if what I said above is correct, you need to use library statements and use statements to bring in the unbound object.

If the internal_memory: fifo is compiled in a library other than "work", you will need to add an entry to your .ini file as well.

If everything is compiled in "work", then anything needed should be found auto magically.

You may have to compile the coregen library as well. You should be able to find it in the Xilinx application directory. If you compile it into the work directory, it should be found.

Far as I know there are no special modelsim versions that would make your problems go away.

Hope that helps

Sckoarn
 

Is this the problem with all the versions of modelsim?
Because the timsim, xlinxcorelib and unisim are the default libraries which should be loaded everytime a design a run..they are the default libraries provided but they do not run when the code is loaded..they need to manually loaded ie scripted to run....always u load a design in modelsim?
 

snehanidhi,

The entity that contains the IP you are using, needs to have Library and Use directives, to enable the compiled item to know all the libs to look in for objects.

something like

library timsim;
use timsim.all;

for each library needed. Once these statements are added and recompiled, things should work differently.

Also, since the libs are being found by the simulator, I assume the .ini file has path to where they are. This should show that the libs are not located in the local work directory.

Sckoarn
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top