[HELP] What is wrong with my code? Syntax Error provided. (VERILOG using MODELSIM)

SYNTAX ERROR:

# ** Error: C:/Documents and Settings/saru unit 2/Desktop/fx.v(72): near "#": syntax error, unexpected '#'
# ** Error: C:/Documents and Settings/saru unit 2/Desktop/fx.v(110): near "#": syntax error, unexpected '#'
# ** Error: C:/Documents and Settings/saru unit 2/Desktop/fx.v(145): near "#": syntax error, unexpected '#'
# ** Error: C:/Documents and Settings/saru unit 2/Desktop/fx.v(179): near "#": syntax error, unexpected '#'


NOTE: I'm using the DELAY STATEMENT "#(delay to on, delay to off)". I guess there exist a mistake in its syntax.

PICTURE OF LINE OF THE ERRORS:

CHANGE HXXP TO HTTP

hxxp://img593.imageshack.us/i/syntax.jpg/

---------------------------------------------------------------------------------


module trafficlight(
ONorth_greenLEFT,
ONorth_redRIGHT,
OSouth_redLEFT,
OSouth_greenRIGHT,
OEast_redUP,
OEast_greenDOWN,
OWest_greenUP,
OWest_redDOWN,
ONorth_redLEFT,
ONorth_greenRIGHT,
OSouth_greenLEFT,
OSouth_redRIGHT,
OEast_greenUP,
OEast_redDOWN,
OWest_redUP,
OWest_greenDOWN,
IaddressTRAFFIC
);
//INTERNAL VARIABLES

wire a;
wire b;
wire c;
wire d;

// INPUT PORT
// INPUT SYNTAX [HIGHEST VALUE : LOWEST VALUE]

input [4:1] IaddressTRAFFIC;

// OUTPUT PORTS

output ONorth_greenLEFT;
output ONorth_redRIGHT;
output OSouth_redLEFT;
output OSouth_greenRIGHT;
output OEast_redUP;
output OEast_greenDOWN;
output OWest_greenUP;
output OWest_redDOWN;


output ONorth_redLEFT;
output ONorth_greenRIGHT;
output OSouth_greenLEFT;
output OSouth_redRIGHT;
output OEast_greenUP;
output OEast_redDOWN;
output OWest_redUP;
output OWest_greenDOWN;

//CASE STATEMENT IS USED TO SELECT THE STATUS OF TRAFFIC
//WHILE STATEMENT IS USED FOR LOOPING
//DELAY STATEMENT SYNTAX: #(DELAY TO ON, DELAY TO OFF)
//assign #(0,500) ONorth_greenLEFT=1; DELAY IN CONTINUOS ASSIGNMENT

case (IaddressTRAFFIC)
1: // NORMAL TRAFFIC
initial
begin
a = 0;
while( a <= 500 )
begin

a = a + 1;

// NORTH AND SOUTH GO: NORMAL : 500 COUNTS

assign #(0,500) ONorth_greenLEFT=1;
assign #(0,500) ONorth_redRIGHT=1;
assign #(0,500) OSouth_redLEFT=1;
assign #(0,500) OSouth_greenRIGHT=1;
assign #(0,500) OEast_redUP=1;
assign #(0,500) OEast_greenDOWN=1;
assign #(0,500) OWest_greenUP=1;
assign #(0,500) OWest_redDOWN=1;


// WEST AND EAST GO: NORMAL : 500 COUNTS

assign #(500,1000) ONorth_redLEFT=1;
assign #(500,1000) ONorth_greenRIGHT=1;
assign #(500,1000) OSouth_greenLEFT=1;
assign #(500,1000) OSouth_redRIGHT=1;
assign #(500,1000) OEast_greenUP=1;
assign #(500,1000) OEast_redDOWN=1;
assign #(500,1000) OWest_greenDOWN=1;
assign #(500,1000) OWest_redUP=1;

end
end


2: //TRAFFIC NORTH and SOUTH

initial
begin
b = 0;
while( b <= 500 )
begin

b = b + 1;


// NORTH AND SOUTH GO: TRAFFIC : 1000 COUNTS

assign #(0,1000) ONorth_greenLEFT=1;
assign #(0,1000) ONorth_redRIGHT=1;
assign #(0,1000) OSouth_redLEFT=1;
assign #(0,1000) OSouth_greenRIGHT=1;
assign #(0,1000) OEast_redUP=1;
assign #(0,1000) OEast_greenDOWN=1;
assign #(0,1000) OWest_greenUP=1;
assign #(0,1000) OWest_redDOWN=1;

// WEST AND EAST GO: NORMAL : 500 COUNTS

assign #(1000,1500) ONorth_redLEFT=1;
assign #(1000,1500) ONorth_greenRIGHT=1;
assign #(1000,1500) OSouth_greenLEFT=1;
assign #(1000,1500) OSouth_redRIGHT=1;
assign #(1000,1500) OEast_redDOWN=1;
assign #(1000,1500) OWest_greenDOWN=1;
assign #(1000,1500) OWest_redUP=1;
end
end


3: //TRAFFIC WEST and EAST
initial
begin
c = 0;
while( c <= 500 )
begin

c = c + 1;


// NORTH AND SOUTH GO: NORMAL : 500 COUNTS


assign #(0,500) ONorth_greenLEFT=1;
assign #(0,500) ONorth_redRIGHT=1;
assign #(0,500) OSouth_redLEFT=1;
assign #(0,500) OSouth_greenRIGHT=1;
assign #(0,500) OEast_redUP=1;
assign #(0,500) OEast_greenDOWN=1;
assign #(0,500) OWest_greenUP=1;
assign #(0,500) OWest_redDOWN=1;

// WEST AND EAST GO: NORMAL : 500 COUNTS

assign #(500,1500) ONorth_redLEFT=1;
assign #(500,1500) ONorth_greenRIGHT=1;
assign #(500,1500) OSouth_greenLEFT=1;
assign #(500,1500) OSouth_redRIGHT=1;
assign #(500,1500) OEast_greenUP=1;
assign #(500,1500) OEast_redDOWN=1;
assign #(500,1500) OWest_greenDOWN=1;
assign #(500,1500) OWest_redUP=1;

end
end

4: //TRAFFIC NORTH, SOUTH, WEST, EAST
initial
begin
d = 0;
while( d <= 500 )
begin

d = d + 1;

// NORTH AND SOUTH GO: NORMAL : 500 COUNTS

assign #(0,500) ONorth_greenLEFT=1;
assign #(0,500) ONorth_redRIGHT=1;
assign #(0,500) OSouth_redLEFT=1;
assign #(0,500) OSouth_greenRIGHT=1;
assign #(0,500) OEast_redUP=1;
assign #(0,500) OEast_greenDOWN=1;
assign #(0,500) OWest_greenUP=1;
assign #(0,500) OWest_redDOWN=1;


// WEST AND EAST GO: TRAFFIC : 500 COUNTS

assign #(500,1000) ONorth_redLEFT=1;
assign #(500,1000) ONorth_greenRIGHT=1;
assign #(500,1000) OSouth_greenLEFT=1;
assign #(500,1000) OSouth_redRIGHT=1;
assign #(500,1000) OEast_greenUP=1;
assign #(500,1000) OEast_redDOWN=1;
assign #(500,1000) OWest_greenDOWN=1;
assign #(500,1000) OWest_redUP=1;

end
end

//default: $display("Error in SEL");
// DEFAULT IS AN OUTPUT IN CASE VALUE SELECTED IS NOT 1-4

endcase


endmodule

The delay syntax is correct, as far as I'm aware of, but you are using continuous assignments in the wrong place (inside a case construct).

I fear, you also misunderstood the purpose of Verilog iteration loops. They are not generating a sequence in time.

Consult your Verilog text book in this regard, or ask the guy who issued the exercise.

Thanks. I had difficulty understanding Verilog because the teacher did not give classes on it. He gave us 2 days to code and learn using free resources on the internet.

Most Verilog code is intended for synthesis. I guess, you also want to try your code in a real hardware.

Verilog delay statements are for simulation only and can't be synthesized in hardware. There purpose is the simulation of small (nanseconds range) logic delays. They also play a role for testbenches, in this case, you may want to set seconds delays for a traffic light stimulus.

To generate delays in hardware, you need a clock input. Mostly, it's rather high frequency (MHz range), so it has to be divided down to get visual delays. All timing for your design should be generated by counting clocks. But not in a for loop iteration, you have to use edge sensitive always blocks.