VHDL counter circuit question

I am planning to design a circuit which is calculating the linear movement to a wheel, with input from encoders. Sine I am new to VHDL I have designed a simplified circuit for testing the “code” at a Altera DE2-70 evaluation board.
I currently having a hard time to design this simple up/down counter (with push buttons as control to the up/down value). The problem is random view of number at the BCD when the buttons are activated. My code is as follows:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
port
(
a :IN STD_LOGIC;
b :IN STD_LOGIC;
result :OUT UNSIGNED(6 downto 0));
end entity;

Architecture rtl of test is
signal n6 : UNSIGNED (3 downto 0);

begin
PROCESS(a,b)
begin
IF (a = '1' AND n6<"1111" ) THEN
n6<=n6 + 1;
ELSIF (b='1' AND n6>"0000") THEN
n6<=n6 - 1;
END IF;
--Seven segment view
Case n6 IS
WHEN "0000"=>
result<="1000000" ;
:
:
:
result<="0001110";
END CASE;
END PROCESS;
END rtl;

Could it be the “bouncing” that occurs when the button is activated that cause the trouble?
Have I understood the PROCESS keyword right when I compare this to raising a event in other programming language? I.e when one of the variables in the sensitivity list changes value, the contents of the process is executed.

the process is missing n6 from the sensitivity list. But you also have problems because you have created an asynchronous counter. Because it has no time base to go from, when you press the button, it will count as fast as the propogation delay, so will increment by one every couple of nanosecons. This is the main reason it appears random when you press the button. You need a clock input, or at least a rising edge detector (not the rising_edge function, that is for clocks) on a and b.

TrickyDicky is right.. Just make these changes

IF ( rising_edge(a) AND n6<"1111")

IF ( rising_edge(b) AND n6<"0000")

it should work now...

You can visit my blog if you like to do some basic projects: All About VHDL Codes, PCB Designing and AVR

I said not to use the rising_edge function on any signal unless it is a clock.

It may work here, but is generally bad practice and a bad idea.

TrickyDicky said:

I said not to use the rising_edge function on any signal unless it is a clock.

It may work here, but is generally bad practice and a bad idea.

Click to expand...

But to perform a counter function with counting only when you want(which actually will be manual delay) you are going to require a clock.. or else it will increment by its own and that too cause error due to propogation delays of diffrent gates and muxes.. Adding rising_edge function will add a Dflipflop and also in the program written above 'a' and 'b' (Concidering presence of Hardware debouncing ckt) are manual clock i/p...

If you dont want to use them as clock i/p you can give slower clock using clock divider to dff and use 'a' and 'b' as Enable of dff...

when you will press 'a' button it will increment at rate of i/p clock..

but for this kind of circuit additional LUTs will be used while for previous one the no. of gates used will be less..

---------- Post added at 15:38 ---------- Previous post was at 15:32 ----------

@TrickyDicky: I didnt understood what you mean by 'rising edge detector'.. I am a beginner so dont know much about it.. But it will great help if you illustrate it... []

For a rising edge detector you need a clock. You register your input A and compare the registered version to the input, so you can detect edges

if rising_edge(clk) then
if a = '1' and a_r = '0' then --detect a rising edge on a

etc.

TrickyDicky said:

For a rising edge detector you need a clock. You register your input A and compare the registered version to the input, so you can detect edges

if rising_edge(clk) then
if a = '1' and a_r = '0' then --detect a rising edge on a

etc.

Click to expand...

so what if i replace 'clk' by 'a' and write counter code below that... ;-)

Result: Usage of Gates on FPGA reduced.

Using non-clocks as clocks can mean setup and hold times are violated. In this case, because the circuit is simple you may get away with it. But for larger designs it can cause serious issues, so I wouldnt recommend it as a habit to get into.

I got it now..

jimmy_tag said:

I got it now..

Click to expand...

Tnx for replays,

Jimmy:
I watched your blog and notice that you have experience with altera DE board. How do you assign the clock? Are you using the pin assignment to assign the clock to a input, or is there a keyword that include the clock in quartus?

My new code is as follows (do not work, nothing happens when the buttons is activated)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
port
(
Clock :IN STD_LOGIC;
a :IN STD_LOGIC;
b :IN STD_LOGIC;
result :OUT UNSIGNED(6 downto 0));

end entity;

Architecture rtl of test is
signal n4,n5,n6 : UNSIGNED (3 downto 0);
signal n1,n2 : STD_LOGIC;

begin
PROCESS(a,b,n6,Clock)
begin
IF rising_edge(Clock) THEN
IF (a = '1'AND n1='0' AND n6<”1111” ) THEN
n6<=n6 + 1;
n1<='1';
ELSIF (a='0'AND n1='1') THEN
n1<='0';
END IF;
IF (b='1'AND n2='0' AND n6>”0000”) THEN
n6<=n6 - 1;
n2<='1';
ELSIF (b='0' AND n2='1') THEN
n2<='0';
END IF;
END IF;

Case n6 IS
WHEN "0000"=>
result<="1000000" ;
:
:
WHEN "1111"=>
result<="0001110";
END CASE;
END PROCESS;
END rtl;

@jdh_1984: Check out the DE board manual you will see the pins which are factory assigned with various functions. And there is no such keyword Clock in Quartus.

About your code, see you havent assigned any value to n1, n2. So the process wont execute untill you assign proper values to signals. Actually i think there is no requirement of n1 or n2, just remove them and try the code.

Dont concider VHDL as C\C++. Thinks as like how will the gates works as you design a code. VHDL is used to designed hardware, think in that way and you will get it.

and you are missing a reset ...