Difference between .sdc and .sdf files

Hi,
Can anyone explain me the difference between a .sdc file and .sdf file?
What information do each contain?

Thanks

The SDF file extension can be used as a schedule data file, a source definition file, a standard data format, a standard delay format, and a system data format.

The SDF file extension is a data file with a fixed length of ASCII, when it works as a system data format file. But when it functions as the standard delay format, the SDF file extension becomes an OVI standard and it is used to represent and interpret the different timing of data, which will be used for the process of electronic designing.

The SDF file extension may also function differently when used as a standard data format. This becomes a readily available system of documentation, which is designed and created based on a specific comprehensive markup language. The file extension can generate different output files using various formats, which are all based, from one document source. Included to the supported formats of the SDF file extension being a standard data format are the PostScript, HTML, man pages, PDF, LateX, POD, SGML, MIF, Windows Help, plain text, MIMS HTX, RTF, and F6 help.

Another specific function of the SDF file extension with an SDF acronym is as a Soundweb Designer File. The Soundweb Designer program is created for lay outing a set of different Soundweb units, which will all be used for a specific design and defining of the different networks connections running between them. With the SDF file extension, each of these units will be used in defining the audio processing objects. These will all be present in the user's computer system.

There are also other uses for the SDF file extension that does not have the SDF acronym, just like its function as a mail storage file for the MSN Local Machine. The file extension will be responsible for renaming the files from specific MSN accounts. These renamed files will have the SDF file extension and will be saved in the My Documents folder.

---------- Post added at 23:51 ---------- Previous post was at 23:43 ----------

Design Compiler generates SDC files (Synopsys Design Constraints)

It is clear from the replies here that many of you have not done a real chip design. You do need a "seed" sdc file which defines clocks and input/output delays for the synthesizer. It should also have false paths, multicycle paths, and generated clocks. After synthesis you generate a NEW sdc from DC, you get many new paths generated, lots of nets. You run Primetime on this netlist and read in that sdc. After all the false timing paths have been analyzed and constraints are updated, you write a new sdc which is given to PnR. Primetime is run several times: post-synth, after FloorPlanning & Global PnR, after CTS & Detailed Route, and after Parasitic extraction.

SDC - Synopsys Design Constraints
This file is used for all implementation tools starting from synthesis, timing analysis, place&route,dft,fpga..etc. This is very important file to ensure proper operation of your design, fpga, silicon

SDF - Standard Delay Format
Used to convey the timing information of a design after implementation (it can be generated at all of above steps). This is what says whats the delay at each cell, net, node. This is exported to do the simulation of design and to find if the design is operating at the Frequency without any setup/hold violations.

Hi,

SDC in ASIC design flow corresponds to Synopsys design constraints file. It is a Tcl based format-constraining file. It provides the timing information, constraints regarding the design to the tool. The tool uses the SDC file when performing timing analysis. This is a file which is initially given by the Designer at Synthesis stage for tools like Design compiler. It comprises of information regarding clock period, clock uncertainity, clock latency, input delay and output delay, flase paths, multicycle paths, transition values etc. These values will help in performing the initial timing analysis for finding any violations in our design. After synthesis at every subsequent step of the design flow SDC file will be written out from the tool so that it can be given as input to the tools in next step till PnR. This provides the tools for next step to know what constraints have been applied on the design in the previous step.

In PnR as we will be placing the cells and routing these cells we can actually know what will be the cell and net delays. So when we do timing analysis at this stage, Primetime which is the sign off tool for timing will write out the SDF for gate level simulation purpose. SDF will be used by tools in previous stages of ASIC design flow to back-annotate the interconnect delay. This helps in performing a more accurate timing analysis for violations as it takes into account specific cell and interconnect delays. A synthesis can use this information to improve the logic structure. After all these optimizations we will do timing analysis again on Primetime to generate the refined timing report.

So, SDC is a user constraint file which can be written out from the tools at each step and SDF is a tool generated back-annotated file for generating more accurate timing reports and do necessary optimizations on the design.

Hope it helps...

Hi Srinivasan,

You can see the details regariding SDC in the following blog.
VLSI concepts: Synopsys Design Constraints (SDC) Basics