Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

implementing a queue in vhdl

Status
Not open for further replies.
H

hitech

Newbie level 4
Joined
Sep 27, 2010
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,310
Hi

i Am new to VHDL and just start working on it.

i want to implement a queue in VHDL which can store data from bit stream.

does anyone know how to do that.

thanks in advance
hitech
 

hitech,

You could take the bit stream, convert it to words, 8-32 bits. You can then store those in a FIFO and take them out on the output side of the FIFO as needed. A FIFO can be implemented in a duel port block RAM. One side is writing the bits, converted to words, and the other side is reading them as needed. This will work as long as your rate of reading is more than your rate or writing.

Here is a link to a web search, FIFO VHDL implementation
VHDL Code


Sckoarn
 

""You could take the bit stream, convert it to words, 8-32 bits.""
can you please elaborate this?? for conversion do we need to store is some where and from there we have to take Dword or a byte??? or how can we proceed this?

Thanks
hitech
 

Hitech,

I only say conver to words because they are easy to store in a FIFO but there is no reason why you could not use a one bit wide FIFO. Just that words (8-32 bits) will use the block RAM more efficiently. So it all depends on if your FPGA is used up, you may want to pack things in more.

To convert a bit stream into words, for each bit that comes in, write that bit to an index in the word. When you have enough bits, ie. counter went to max, you can load the word into the FIFO with a simple write operation.

Code: 
signal  word  :  std_logic_vector(7 downto 0);

gen_word:
  process(rst, clk)
    variable i   :  integer
  begin
    if(rst = '1')
      i  := 0;
      write_fifo  <=  '0';
    elsif(clk'event and clk = '1' and "valid") then
      write_fifo  <=  '0';
      word(i)  <=  input_bit;
      i  :=  i + 1;
      if(i = 8) then
        i := 0;
        write_fifo  <=  '1';
      end if;
    end if;
end process gen_word;
A short "incomplete" bit of code above should help some

Sckoarn
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top