Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] query regarding transition voilation ??

Status
Not open for further replies.

hari151087

Newbie level 6
Joined
Jan 21, 2011
Messages
11
Helped
0
Reputation
2
Reaction score
0
Trophy points
1,281
Location
Bangalore, India
Activity points
1,335
why there is a need to clear transition violation even after Timing is cleared ???

and

Do we need to consider tran voilation even in hold mode??
 

If the transition viol goes beyond what the timing library is characterized at, timing analysis tools have to extrapolate the delay curve upon the delay calculation, which makes the timing inaccurate.
You have to keep it at least within the max transition defined in the timing library.
 
Last edited:
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top