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Design Techniques for Low Power

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rohit_singh1

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I ran across one blog that talks about Designs for Low power. Among others, three techniques caught my attention and I don't seem to find the reason - why/how do these three techniques help in low power design:

1) run high frequency signals through few hierarchies
2) choose gray coding instead of binary coding
3) use multiplexer instead of tri-state bus

Can anybody please explain me the reason for these three techniques? Any help is appreciated.

TIA
 

Power = cv^2f* T, where T is the toggle rate = on average the percentage of the nets that are toggling at any time; f is the clock frequency; v is supply voltage; and c is the logic gate capacitance.

With that in mind, it is easy to understand that 1. high frequency nets dissipate high power, by letting it go thru as few hierarchies as possible, it will reduce the toggle rate; 2. gray coding reduces toggle rate.

3 is different issue. Internal tristate bus, if not handled properly, will cause floating nets, which will lead to power leakage.

Hope it helps.
 
as far as I know, you can use many techniques from RTL-synthesis-implemention!
 

Frankly, I don't believe all those ideas suggested from this "blog" saves much power. It's just for discussion sake, but not practial in many situations. Most of the power nowadays comes from clock networks.
Do clock gating and use high Vt cells and be done with it.
 
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Frankly, I don't believe all those ideas suggested from this "blog" saves much power. It's just for discussion sake, but not practial in many situations. Most of the power nowadays comes from clock networks.
Do clock gating and use high Vt cells and be done with it.

Thanks. Could you please explain little bit about high Vt cells and how they help in low power design ?
 

High Vt cells are those which threshold higher than normal cells so that the leakage will be less. The leakage will be less because they require more voltage to form the channel(Vgs>Vt) so higher the threshold voltage the more time they take to form the channel. this impacts the speed of operation these circuits but will help in reducing the leakage current which is becoming a major concern in ASIC along with dynamic power consumption.

We can even use multi Vd and muti Vt cells for reducing power consumption in circuits along with clock gating. New methods such as power gating using "retention registers" and "signal isolation" are also under consideration these days, though power gating poses lot of interesting challenges.
 
Thanks! Also, I read in Wikipedia that there is about 70% lower power consumption in asynchronous designs as compared to synchronous designs -- Could you please explain why ?

I can see that there is this notion of switching activity related to power consumption. But how do you make sure that asynchronous designs have less switching activity that synchronous designs ? or am I going in a completely wrong direction ?
 

Thanks! Also, I read in Wikipedia that there is about 70% lower power consumption in asynchronous designs as compared to synchronous designs -- Could you please explain why ?

I can see that there is this notion of switching activity related to power consumption. But how do you make sure that asynchronous designs have less switching activity that synchronous designs ? or am I going in a completely wrong direction ?

This is true. Asynchronous design usually consumes less power than synchronous design. The reason lies in the the nature of the circuit. Synchronous logic uses flip flops, and these flip flops consume quite some power, even if the design is in idle state (the clock is running, and their data inputs are held steady.)

Asynchronous design does not use clock to synchronize the data propagation. A particular gate is activated only when its inputs have activities. When circuit is in idle state, no nets will toggle. The switching activity is less in general, than the synchronous counterpart.

Why don't we just all do asynchronous design then? Well, synchronous design theory is matured, and we have all kinds of EDA tools to help us to handle multi-million gates design. Asynchronous design, on the other hand, is still mostly relying on manual efforts.
 
Please go through this link
**broken link removed**

In the same wiki page it is quoted "Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of High-k dielectrics)."

This explains that as soon as data changes it will be evaluated without waiting for any global clock..
Moreover as Asynchronous circuits do not use a global clock all the transistions that might take place on the clock will be redundant and power will be reduced(P=activity factor* C{V}^{2}f ). Though Synchronous is preferred as it results in better controlling of the circuit.

Around 4-5 yrs back EPSON successfully launched a asynchronous CPU those details are at
**broken link removed**

Hope it is helpful
 
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