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Muxed clocks Problem during synthesis using DC

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akp494

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Hi
In my RTL I have two clocks going as an input to a MUX. One is 500 MHz clock and another is 12 MHz. When select line of MUX is '0' then 500 MHz clock is selected. The MUX output is supplied as clock to some of the modules.

Here are the few observations I made when i did synthesis using DC on this design.

1) First time I didn't tell the tool that there is clock gating in my design. But I specified both the clocks. DC didn't report any timing violations. Area came around 53 K. Non-Combinational area being 24K and the rest is combinational area. But I can see both 500 MHz and 12 MHz clock groups in the timing report.

2) Second time I removed the MUX from RTL and connected 500 MHz clock directly to all the modules and synthesized the design. There were no timing violations reported but surprisingly area went upto 90K which I think is huge increase.

3) Third time I hard instantiated the MUX cell in the RTL . This MUX cell was taken from the target library. I synthesized this design and used set_case_analysis. I did a case analysis by setting the select line value to '0' so that 500 MHz clock is selected. Now also there are no timing violations reported but area came around 78K.

In all the above cases non-combinational area remained the same at 24K. Only combinational area was changing.


I am really confused with these strange results from DC. Can someone please explain me why these strange results are reported by DC .


Thanks in advance.
Prasad
 

Hi akp494:

Your design is Multiplexed clock, neither Gated clock nor Multiple clock.

In the first time, you use Multiple clock, you know dc will report timing of

all clock, so you get both of them.

In the second time, you use single clock.

At last you do the right thing--Multiplexed clock.

You know dc will use different strategy for different situation, that's why

you got different results.

wang1
 

Hi Wang1

Thanks for the response.
But my question was how did the area increse so much in the case2. Is there any specific reason for that.
 

in 2nd case, you have a high frequency for all the path, some of which are using slow clock in 1st case.
for there paths they have much higher requirement comparing with in 1st case, they have to choosing high drive cell, that means bigger ones. so ........that is why the area increased so much, in my oppinion.

regards

and if i am not wrong 12Mhz clock is for test
 

in 3rd case , I guess you didn't add set ideal clk, set dont touch network clk500MHz

Would you response my question?
 

Hi Roger
Even in the 3 rd case I did set all the necessary things like set_dont_touch etc....on the clock .
 

pls set all the necessary constraint on case2 & case3
so that we can afford to compare in the same condition.
at case3 pls set the clock500MHz constraint after mux.

This is a interesting issue.
wait to get your response

one thing I am curious's that in what process or design will make 500MHz such
high freq clk without any timing violation?
 

I can understand the result different between case1 and case2. it is because of the clock frequency rose.
The intresting is case3. Waiting for explain!!
 

Case 3 is equivalent to case 1:

while in case 2 all paths (12 MHz paths too) were clocked at high frequency (and the size willl increase), in case 3 only the paths originally clocked at 500 MHz will be at 500 MHz (it's a case analisys, but her effect is limited to the MUX and his logic cone)...
 

it's better to separate CLOCK MUX LOGIC into a

individual module, then other module will has only one clock,

you can synthesize them separately, it's very easy.





akp494 said:
Hi
In my RTL I have two clocks going as an input to a MUX. One is 500 MHz clock and another is 12 MHz. When select line of MUX is '0' then 500 MHz clock is selected. The MUX output is supplied as clock to some of the modules.

Here are the few observations I made when i did synthesis using DC on this design.

1) First time I didn't tell the tool that there is clock gating in my design. But I specified both the clocks. DC didn't report any timing violations. Area came around 53 K. Non-Combinational area being 24K and the rest is combinational area. But I can see both 500 MHz and 12 MHz clock groups in the timing report.

2) Second time I removed the MUX from RTL and connected 500 MHz clock directly to all the modules and synthesized the design. There were no timing violations reported but surprisingly area went upto 90K which I think is huge increase.

3) Third time I hard instantiated the MUX cell in the RTL . This MUX cell was taken from the target library. I synthesized this design and used set_case_analysis. I did a case analysis by setting the select line value to '0' so that 500 MHz clock is selected. Now also there are no timing violations reported but area came around 78K.

In all the above cases non-combinational area remained the same at 24K. Only combinational area was changing.


I am really confused with these strange results from DC. Can someone please explain me why these strange results are reported by DC .


Thanks in advance.
Prasad
Click to expand...
 

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