[SOLVED] Layout of active device and passive device

Hi guys,

When i am doing floorplan my manager advises me to put active device(such as mosfet) away from bondpad. Instead, put passive device(such as cap and resistor) around the bondpad. He said active device is nearer to the surface of the chip comparing to the passive device.
My question is:
1. Is it right of what he said?
2.Why passvie device can be near the bondpad?

Regards,

Ming

It depends on which kind a block do u designing...I just can guess that you are working on I/O blocks(you are talking about pads;-))..So YOU can't put any sensitive device under or near pads(e.g ESD blocks)...so in this case your advisor is right...

fuxinmingming said:

... active device is nearer to the surface of the chip comparing to the passive device.
My question is: 1. Is it right of what he said?

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Don't think so. Could be a misunderstanding.

fuxinmingming said:

2. Why passive device can be near the bondpad?

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In the bondring area, both electrical and mechanical stress occurs. So there shouldn't be critical devices (means: these which are sensitive to ESD, or those responsible for high accuracy) too close, independent of being active or passive. However, MOS devices (FETs=active, MOSCAPs=passive) are more sensitive to ESD events than non-MOS devices like resistors, non-MOS caps, inductors, or any pn-junctions.

Thank you, erikl. I just put moscap and resistor and ESD blocks near the bondpad.

Regards,

Ming

fuxinmingming said:

I just put moscap ... and ESD blocks near the bondpad.

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Then don't let the MOSCAP have any connection to the ESD block :!:

The only passive devices that can be "nearer the bond pad" in the vertical sense are the MIM capacitor and Metal Inductor. Depending on how close is close, these devices would not care. Resistors, PIS capacitors, MOSFETs, BIPOLARs, varactors, etc are all close to the silicon surface. At technologies < 0.22um, they are at and below the silicon surface as a result of using Shallow Trench Isolation (STI).
For a standard foundry, a rule of thumb is roughly 1um between metal layers. So a 4 layer metal process means that the top metal is 4um vertically away from the silicon surface where most of the active components are built (but this is a very rough approximation).
However in multi layer technologies, it is possible to place active circuitry under the bond pad, when the bond pad is so far away vertically.
So for a 6 layer metal process, the top layer is close to 6um away and will not affect circuitry at the silicon surface. In reality it is closer to 5um but this may still be good enough margin if the circuitry below the pads is not highly sensitive to matching (layout).

Hi colbhaidh,

Thanks a lot. It helps me a lot.

Regards,

Ming