Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

PFET Self-turn ON issue

Status
Not open for further replies.
J

jeetz_mail

Newbie level 6
Joined
Jan 25, 2011
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,376
Hi
Please see the attached file for my circuit.

Circuit description:
I am trying to charge a battery through a PFET switch, Q2. When charger is connected, it pulls Vcharger high, which causes the inverter output to be low and turns Q2 ON. The problem is that when the charger is removed, Q2 switch will feed back VBAT to Vcharger, therefore, reinforcing the inverter output to be low and keeping Q2 ON forever.

Any ideas on how to solve this issue?

Thanks
Jeet
 

Attachments

  • circuit.doc
    24 KB · Views: 99

Post it as a propriate picture format, Then I might help.
 

Try to add pull low current at VCHARGER and use resistor divider for INVERTER gate.
 

jeetz_mail said:
Hi
Please see the attached file for my circuit.

Circuit description:
I am trying to charge a battery through a PFET switch, Q2. When charger is connected, it pulls Vcharger high, which causes the inverter output to be low and turns Q2 ON. The problem is that when the charger is removed, Q2 switch will feed back VBAT to Vcharger, therefore, reinforcing the inverter output to be low and keeping Q2 ON forever.

Any ideas on how to solve this issue?

Thanks
Jeet
Click to expand...
If the battery is positive voltage and negative referred to ground, I feel that the way the P-MOSFET is applied is wrong and for a better understanding, please study a primer as below.
**broken link removed** 1st part is linked therein
all the best
 
Last edited:

PMOS is correct. In most of charger IC design, it uses Power PMOS. However, in Jeet's schematic, the charging current is not well controlled. It might be not good for battery lifetime.
 

the source of Pmosfet is to see the positive side( here the charger side- )provided the negativve grounding is adopted.
that is why I commented that the way in which the diagram is configured is wrong .
 

Prototyp_V1.0 said:
Post it as a propriate picture format, Then I might help.
Click to expand...

Sure. Please click on the following link to see the circuit image.

Imageshack - circuitn.jpg

Thanks.
Jeet

---------- Post added at 10:00 ---------- Previous post was at 09:58 ----------

Hello mvs

The reason I have "PFET Source" on the battery side is that when the charger is removed, VBAT can pull the PFET gate high to turn it off. When the charger is removed, Vcharger is gone, so it cannot control the PFET gate. Please see the circuit image in the link below:

Imageshack - circuitn.jpg

Thanks
Jeet

---------- Post added at 10:02 ---------- Previous post was at 10:00 ----------
leo_o2 said:
Try to add pull low current at VCHARGER and use resistor divider for INVERTER gate.
Click to expand...

Hello Leo

I am having hard time visualizing what you have tried to say. Is it possible for you to add an image or attachment showing your idea.
Thanks
Jeet
 

please see Fig3 on page2 of attached pdf file . this is a way how to use p-mosfet for power switching.
the battery charging current has some how to be limited by you.
 

Attachments

  • 70611.pdf
    46.8 KB · Views: 91

mvs sarma said:
please see Fig3 on page2 of attached pdf file . this is a way how to use p-mosfet for power switching.
the battery charging current has some how to be limited by you.
Click to expand...

Hi

I recognize that I wasn't connecting the Source of the PFET on the high side.

Even if I attach the source on the high side (see the following link), the problem still remains. When the charger is removed (notice that PFET is ON at that instant), the PFET will feed back VBAT to Vchrg and keep itself ON forever through the inverter.

ImageShack® - Online Photo and Video Hosting

Any ideas to solve that issue?
Thanks
Jeet
 

jeetz_mail said:
Any ideas to solve that issue?
Click to expand...

I think you should keep your old configuration

... and add a medium/low value pull-down resistor (~10kΩ) from the VCHARGER--D(3) connection to GND.

Instead of the INVERTER, a single nMOSFET should be enough, because R32 pulls up anyway during the inactive state.
 

erikl said:
I think you should keep your old configuration

... and add a medium/low value pull-down resistor (~10kΩ) from the VCHARGER--D(3) connection to GND.

Instead of the INVERTER, a single nMOSFET should be enough, because R32 pulls up anyway during the inactive state.
Click to expand...

Hello Erikl

I am currently in the process of the prototyping the following circuit:
ImageShack® - Online Photo and Video Hosting

However, my hunch is that, even with nFET (used as open collector type), PFET will feed back and keep itself on when the charger is removed.

Thanks
Jeet

---------- Post added at 14:57 ---------- Previous post was at 13:29 ----------
jeetz_mail said:
Hello Erikl

I am currently in the process of the prototyping the following circuit:
ImageShack® - Online Photo and Video Hosting

However, my hunch is that, even with nFET (used as open collector type), PFET will feed back and keep itself on when the charger is removed.

Thanks
Jeet
Click to expand...

Ok. So I have tested the following circuit:
ImageShack® - Online Photo and Video Hosting
It didn't work. The PFET would keep itself ON even when the VCharger was removed, as I had expected.
Any more ideas?
- Jeet
 


erikl said:
You didn't insert the resistor between the Drain and GND which I suggested. Perhaps it might help?
Click to expand...

I have a resistor between the DRAIN of PFET and GND. Did you mean the Drain of NFET and Gnd ?
 

No, from the Drain of Q3. But 1MΩ might be too large for pull-down; try 1..10kΩ.

On the other hand, you cannot expect an effective charge control from this circuit, because - during charging - Q3 operates in inverse configuration, and the charge current flows via the parasitic drain-source-diode. The only purpose of this circuit is to avoid possible discharge of the battery via the charger, if it is connected but not powered. However, this could be achieved more easily by a simple diode.

And more: I checked the FDN306P dataSheet: VDSS(max)=-12V is right on -- resp. over -- the limit if you want to charge a 12V accumulator (during the required shut-down phase), because such one will easily reach 14V or more. May be this is the reason that you can't pull down the input node, even with a low-ohmic resistor.

Moreover, VGSS is specified as ±8V, so your FDN306P (or your NMOS) could already be damaged (if you charge an accu ≥8V).
 

it becomes a load and not pull down for gate. i suggested you to follow the fig3 of the pdf, I had uploaded. your sch is still wrong i fear. a gate can be terminated by a smaller resistor like 2.K, 3.3K etc between Gate and source. later the switch could be turned ON by grounding the gate by say 220ohms., this could be done using a N mosfet and triggering with positive voltage like 12V, with a resistor in series, and a high value resistor to ground for that N mosfet gate.
then, when the N fet is ON, the ground goes to pFET input.and switches it ON.
 

mvs sarma said:
it becomes a load and not pull down for gate. i suggested you to follow the fig3 of the pdf, I had uploaded. your sch is still wrong i fear. a gate can be terminated by a smaller resistor like 2.K, 3.3K etc between Gate and source. later the switch could be turned ON by grounding the gate by say 220ohms., this could be done using a N mosfet and triggering with positive voltage like 12V, with a resistor in series, and a high value resistor to ground for that N mosfet gate.
then, when the N fet is ON, the ground goes to pFET input.and switches it ON.
Click to expand...

Thanks. But I can't use the circuit of Fig3 as it won't work in my application.

My application is: I have 3 components to start with, charger, charger connector and battery. I want to connect the battery to the charger connector, only when the charger is connected. When the charger is removed, I want to disconnect the battery from the charger connector as well. In order to detect the charger connection or removal, I only have 1 signal to play with and that is "Vchrg". Now looking at the fig3 that you suggested, "Load can be compared with my battery", "VDD can be compared with the Vchrg" signal. But in fig3, u need an extra signal to control N-channel FET. I don't have that extra signal in my application.

Hope u understand my circuit specifications.

---------- Post added at 10:22 ---------- Previous post was at 10:01 ----------

Hi Erikl, Please see my response in red below [Jeet]
erikl said:
No, from the Drain of Q3. But 1MΩ might be too large for pull-down; try 1..10kΩ.
I have already tried 10k pull down from Drain of Q3 to Gnd, although the sch image shows 1M connected [Jeet]

On the other hand, you cannot expect an effective charge control from this circuit, because - during charging - Q3 operates in inverse configuration, and the charge current flows via the parasitic drain-source-diode. The only purpose of this circuit is to avoid possible discharge of the battery via the charger, if it is connected but not powered. However, this could be achieved more easily by a simple diode.
The problem with using a simple diode is that the voltage drop across diode will be around 0.7V or something. I can not afford that kind of voltage drop across diode. I am trying to charge a 4.2V/25mAh Li/ion battery. Its a small battery with 4.2V maximum voltage. The voltage drop across the diode will be high. [Jeet]

And more: I checked the FDN306P dataSheet: VDSS(max)=-12V is right on -- resp. over -- the limit if you want to charge a 12V accumulator (during the required shut-down phase), because such one will easily reach 14V or more. May be this is the reason that you can't pull down the input node, even with a low-ohmic resistor.
VDSS will never exceed 5V [Jeet]

Moreover, VGSS is specified as ±8V, so your FDN306P (or your NMOS) could already be damaged (if you charge an accu ≥8V).
Click to expand...
VGSS will never exceed 4.2V in my application [Jeet]
 
Last edited:

jeetz_mail said:
Hi Erikl, Please see my response in red below [Jeet]

The problem with using a simple diode is that the voltage drop across diode will be around 0.7V or something. I can not afford that kind of voltage drop across diode. I am trying to charge a 4.2V/25mAh Li/ion battery. Its a small battery with 4.2V maximum voltage. The voltage drop across the diode will be high. [Jeet]
Click to expand...
In your configuration, during charging, Q3 is operated in inverse mode (drain more positive than source), as I already told you above, i.e. the charge current flows via the parasitic diode, which is a Si diode, hence has a voltage drop of ≈0.7V :!:

Perhaps you could use a Schottky diode, which would swallow just about 0.4V, or even a Germanium (transistor used as) diode, which needs only 0.2V (only sensible, if your max. temperature isn't too high, say ≤60°C).

jeetz_mail said:

VDSS will never exceed 5V. [Jeet]
Click to expand...

The FDN306P dataSheet doesn't contain a max. VDSS specification for operation in inverse mode; it could be less than VDSS(max) @ normal mode operation.

In no-charge mode, try to measure the current between Q3 drain and GND via a limiting resistor of ≈1kΩ. This will show you if it is possible to pull-down Q3 drain (with such resistor). If this doesn't work, the FDN306P either cannot block your ≈4V in inverse mode, or it is defective.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top