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flying capacitor modelling during simulation

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allennlowaton

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good day EDA fellows..
I'm having this concern right now. I need a model for my flying capacitors. Is it reasonable to use the PIP model in the process library? The value of that external capacitor is in a minimum of 1uF. I'm not just comfortable using the PIP model because in the first place, that capacitor is external. Any suggestions please..
 

If you simulate in Cadence, pls use cap from analogLib. For spice netlist, pls just use: Cfly node+ node- 1uF. No special model is needed for simulation.
 
leo_o2 said:
Cfly node+ node- 1uF. No special model is needed for simulation.
Click to expand...

thanks leo:
I am using an HSPICE. I have found an RLC approximation model of the capacitor from the net. My application is for white LED driver.
Do I need to include the parasitics in the simulation? My frequency of operation is within 500KHz to 1MHz.
 

If ceramic cap is used, pls add 10~30mohm ESR resistor for it. L can be neglected.
 
thanks again leo:
another thing, I will be having two capacitors for charging and discharging. On a charging phase, those two will be in series.
And I'm afraid that without the parasitics being considered. I can't obtain a total capacitance which is one half of the value of
every capacitor.
 

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