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Help -How to do mixed language design ?

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blooz

blooz

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Coding in VHDL and verilog ....How to do a mixed language project .....Any Good starting tutorial for mixed language design ....

We are currently using verilog and VHDL ......Also Intending to use systemc based design also ....
 

Most tools these days handle mixed language designs seamlessly. You should read the documentaion on any tools you are considering using (simulator, synthesis, place & route, etc. ) Each tool should have docs on mixed language design. One thing to pay attention to is how verilog parameters are passed into VHDL generics, and visa verse. I'm presently working in Altera, and it handles verilog and VHLD without any special constructs. But, using systemC is another story, and each tool is set up differently. Also, look for any vendor turtorials, it's the fastest way to get started.
 
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